[PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Pramod Maurya]

Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML schema, enabling automated
validation with dt-schema.

The new binding covers the same hardware and compatible strings:
  - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
  - xlnx,axi-xadc-1.00.a  (AXI softmacro)
  - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
Changes in v3:
- Move xlnx,channels from properties: to patternProperties: to satisfy
  vendor-props.yaml meta-schema, which requires vendor-prefixed entries
  in properties: to be type: boolean; xlnx,channels is a subnode (object)
  so it belongs in patternProperties:

Changes in v2:
- Fix patternProperties regex to use lowercase hex unit addresses
  (channel@a through channel@f) instead of decimal; correct range
  is now "^channel@([0-9a-f]|10)$"
- Add allOf/if/then conditional to enforce xlnx,external-mux-channel
  is required when xlnx,external-mux is "single" or "dual"

 .../bindings/iio/adc/xilinx-xadc.txt          | 141 ------------
 .../bindings/iio/adc/xlnx,xadc.yaml           | 205 ++++++++++++++++++
 MAINTAINERS                                   |   7 +
 3 files changed, 212 insertions(+), 141 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
 create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml

diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
-	- compatible: Should be one of
-		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
-		  configuration interface to interface to the XADC hardmacro.
-		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
-		  interface to the XADC hardmacro.
-		* "xlnx,system-management-wiz-1.3": When using the
-		  Xilinx System Management Wizard fabric IP core to access the
-		  UltraScale and UltraScale+ System Monitor.
-	- reg: Address and length of the register set for the device
-	- interrupts: Interrupt for the XADC control interface.
-	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
-	  when using the axi-xadc or the axi-system-management-wizard this must be
-	  the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
-	- xlnx,external-mux:
-		* "none": No external multiplexer is used, this is the default
-		  if the property is omitted.
-		* "single": External multiplexer mode is used with one
-		   multiplexer.
-		* "dual": External multiplexer mode is used with two
-		  multiplexers for simultaneous sampling.
-	- xlnx,external-mux-channel: Configures which pair of pins is used to
-	  sample data in external mux mode.
-	  Valid values for single external multiplexer mode are:
-		0: VP/VN
-		1: VAUXP[0]/VAUXN[0]
-		2: VAUXP[1]/VAUXN[1]
-		...
-		16: VAUXP[15]/VAUXN[15]
-	  Valid values for dual external multiplexer mode are:
-		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
-		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
-		...
-		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
-	  This property needs to be present if the device is configured for
-	  external multiplexer mode (either single or dual). If the device is
-	  not using external multiplexer mode the property is ignored.
-	- xnlx,channels: List of external channels that are connected to the ADC
-	  Required properties:
-		* #address-cells: Should be 1.
-		* #size-cells: Should be 0.
-
-	  The child nodes of this node represent the external channels which are
-	  connected to the ADC. If the property is no present no external
-	  channels will be assumed to be connected.
-
-	  Each child node represents one channel and has the following
-	  properties:
-		Required properties:
-			* reg: Pair of pins the channel is connected to.
-				0: VP/VN
-				1: VAUXP[0]/VAUXN[0]
-				2: VAUXP[1]/VAUXN[1]
-				...
-				16: VAUXP[15]/VAUXN[15]
-			  Note each channel number should only be used at most
-			  once.
-		Optional properties:
-			* xlnx,bipolar: If set the channel is used in bipolar
-			  mode.
-
-
-Examples:
-	xadc@f8007100 {
-		compatible = "xlnx,zynq-xadc-1.00.a";
-		reg = <0xf8007100 0x20>;
-		interrupts = <0 7 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&pcap_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-			};
-			channel@1 {
-				reg = <1>;
-			};
-			channel@8 {
-				reg = <8>;
-			};
-		};
-	};
-
-	xadc@43200000 {
-		compatible = "xlnx,axi-xadc-1.00.a";
-		reg = <0x43200000 0x1000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
-
-	adc@80000000 {
-		compatible = "xlnx,system-management-wiz-1.3";
-		reg = <0x80000000 0x1000>;
-		interrupts = <0 81 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
new file mode 100644
index 000000000000..ab6f16109aeb
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XADC and UltraScale System Monitor
+
+maintainers:
+  - Lars-Peter Clausen <lars@metafoo.de>
+
+description: |
+  The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP
+  (Dynamic Reconfiguration Port) interface for communication. Two different
+  frontends for the DRP interface are supported:
+
+    - ZYNQ hardmacro: available only on the ZYNQ family as a hardmacro in
+      the SoC portion of the ZYNQ device.
+    - AXI softmacro: available on all Series 7 platforms as a softmacro
+      with an AXI interface (PG019).
+
+  The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+
+  FPGAs. It is accessed through the Xilinx System Management Wizard IP core
+  via an AXI interface in the FPGA fabric.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,zynq-xadc-1.00.a
+      - xlnx,axi-xadc-1.00.a
+      - xlnx,system-management-wiz-1.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      When using the ZYNQ this must be the ZYNQ PCAP clock.
+      When using the axi-xadc or system-management-wiz this must be
+      the clock that provides the clock to the AXI bus interface.
+    maxItems: 1
+
+  xlnx,external-mux:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: |
+      Selects the external multiplexer mode.
+    enum:
+      - none
+      - single
+      - dual
+
+  xlnx,external-mux-channel:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Configures which pair of pins is used to sample data in external
+      multiplexer mode. This property is required when the device is
+      configured for external multiplexer mode.
+
+      Valid values for single external multiplexer mode:
+        0: VP/VN
+        1-16: VAUXP[0]/VAUXN[0] through VAUXP[15]/VAUXN[15]
+
+      Valid values for dual external multiplexer mode:
+        1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+        2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+        ...
+        8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+    minimum: 0
+    maximum: 16
+
+patternProperties:
+  "^xlnx,channels$":
+    type: object
+    description:
+      List of external channels connected to the ADC. If this property is
+      absent, no external channels are assumed to be connected.
+
+    properties:
+      '#address-cells':
+        const: 1
+
+      '#size-cells':
+        const: 0
+
+    patternProperties:
+      "^channel@([0-9a-f]|10)$":
+        type: object
+        description:
+          Represents an external channel connected to the ADC.
+
+        properties:
+          reg:
+            description: |
+              Pair of pins the channel is connected to.
+                0: VP/VN
+                1: VAUXP[0]/VAUXN[0]
+                2: VAUXP[1]/VAUXN[1]
+                ...
+                16: VAUXP[15]/VAUXN[15]
+            minimum: 0
+            maximum: 16
+
+          xlnx,bipolar:
+            $ref: /schemas/types.yaml#/definitions/flag
+            type: boolean
+            description:
+              If set, the channel is used in bipolar mode.
+
+        required:
+          - reg
+
+        additionalProperties: false
+
+    required:
+      - '#address-cells'
+      - '#size-cells'
+
+    additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        xlnx,external-mux:
+          enum:
+            - single
+            - dual
+      required:
+        - xlnx,external-mux
+    then:
+      required:
+        - xlnx,external-mux-channel
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    /* ZYNQ hardmacro example */
+    adc@f8007100 {
+        compatible = "xlnx,zynq-xadc-1.00.a";
+        reg = <0xf8007100 0x20>;
+        interrupts = <0 7 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&pcap_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+            };
+            channel@1 {
+                reg = <1>;
+            };
+            channel@8 {
+                reg = <8>;
+            };
+        };
+    };
+
+  - |
+    /* AXI softmacro example */
+    adc@43200000 {
+        compatible = "xlnx,axi-xadc-1.00.a";
+        reg = <0x43200000 0x1000>;
+        interrupts = <0 53 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
+
+  - |
+    /* UltraScale System Management Wizard example */
+    adc@80000000 {
+        compatible = "xlnx,system-management-wiz-1.3";
+        reg = <0x80000000 0x1000>;
+        interrupts = <0 81 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75afd16..9b107057ad8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29226,6 +29226,13 @@ F:	Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
 F:	drivers/watchdog/of_xilinx_wdt.c
 F:	drivers/watchdog/xilinx_wwdt.c
 
+XILINX XADC DRIVER
+M:	Lars-Peter Clausen <lars@metafoo.de>
+L:	linux-iio@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
+F:	drivers/iio/adc/xilinx-xadc*
+
 XILINX XDMA DRIVER
 M:	Lizhi Hou <lizhi.hou@amd.com>
 M:	Brian Xu <brian.xu@amd.com>
-- 
2.52.0

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Rob Herring (Arm)]

On Sun, 10 May 2026 04:32:13 -0400, Pramod Maurya wrote:
> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> from the legacy plain-text format to a YAML schema, enabling automated
> validation with dt-schema.
> 
> The new binding covers the same hardware and compatible strings:
>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
> 
> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
> ---
> Changes in v3:
> - Move xlnx,channels from properties: to patternProperties: to satisfy
>   vendor-props.yaml meta-schema, which requires vendor-prefixed entries
>   in properties: to be type: boolean; xlnx,channels is a subnode (object)
>   so it belongs in patternProperties:
> 
> Changes in v2:
> - Fix patternProperties regex to use lowercase hex unit addresses
>   (channel@a through channel@f) instead of decimal; correct range
>   is now "^channel@([0-9a-f]|10)$"
> - Add allOf/if/then conditional to enforce xlnx,external-mux-channel
>   is required when xlnx,external-mux is "single" or "dual"
> 
>  .../bindings/iio/adc/xilinx-xadc.txt          | 141 ------------
>  .../bindings/iio/adc/xlnx,xadc.yaml           | 205 ++++++++++++++++++
>  MAINTAINERS                                   |   7 +
>  3 files changed, 212 insertions(+), 141 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
>  create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml: patternProperties: '^xlnx,channels$' should not be valid under {'pattern': '^\\^[a-zA-Z0-9,\\-._#@]+\\$$'}
	hint: Fixed strings belong in 'properties', not 'patternProperties'
	from schema $id: http://devicetree.org/meta-schemas/keywords.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260510083219.70224-1-pramod.nexgen@gmail.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Pramod Maurya]

Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML schema, enabling automated
validation with dt-schema.

The new binding covers the same hardware and compatible strings:
  - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
  - xlnx,axi-xadc-1.00.a  (AXI softmacro)
  - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
Changes in v3:
- Move xlnx,channels from properties: to patternProperties: to satisfy
  vendor-props.yaml meta-schema, which requires vendor-prefixed entries
  in properties: to be type: boolean; xlnx,channels is a subnode (object)
  so it belongs in patternProperties:

Changes in v2:
- Fix patternProperties regex to use lowercase hex unit addresses
  (channel@a through channel@f) instead of decimal; correct range
  is now "^channel@([0-9a-f]|10)$"
- Add allOf/if/then conditional to enforce xlnx,external-mux-channel
  is required when xlnx,external-mux is "single" or "dual"

 .../bindings/iio/adc/xilinx-xadc.txt          | 141 ------------
 .../bindings/iio/adc/xlnx,xadc.yaml           | 205 ++++++++++++++++++
 MAINTAINERS                                   |   7 +
 3 files changed, 212 insertions(+), 141 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
 create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml

diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
-	- compatible: Should be one of
-		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
-		  configuration interface to interface to the XADC hardmacro.
-		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
-		  interface to the XADC hardmacro.
-		* "xlnx,system-management-wiz-1.3": When using the
-		  Xilinx System Management Wizard fabric IP core to access the
-		  UltraScale and UltraScale+ System Monitor.
-	- reg: Address and length of the register set for the device
-	- interrupts: Interrupt for the XADC control interface.
-	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
-	  when using the axi-xadc or the axi-system-management-wizard this must be
-	  the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
-	- xlnx,external-mux:
-		* "none": No external multiplexer is used, this is the default
-		  if the property is omitted.
-		* "single": External multiplexer mode is used with one
-		   multiplexer.
-		* "dual": External multiplexer mode is used with two
-		  multiplexers for simultaneous sampling.
-	- xlnx,external-mux-channel: Configures which pair of pins is used to
-	  sample data in external mux mode.
-	  Valid values for single external multiplexer mode are:
-		0: VP/VN
-		1: VAUXP[0]/VAUXN[0]
-		2: VAUXP[1]/VAUXN[1]
-		...
-		16: VAUXP[15]/VAUXN[15]
-	  Valid values for dual external multiplexer mode are:
-		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
-		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
-		...
-		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
-	  This property needs to be present if the device is configured for
-	  external multiplexer mode (either single or dual). If the device is
-	  not using external multiplexer mode the property is ignored.
-	- xnlx,channels: List of external channels that are connected to the ADC
-	  Required properties:
-		* #address-cells: Should be 1.
-		* #size-cells: Should be 0.
-
-	  The child nodes of this node represent the external channels which are
-	  connected to the ADC. If the property is no present no external
-	  channels will be assumed to be connected.
-
-	  Each child node represents one channel and has the following
-	  properties:
-		Required properties:
-			* reg: Pair of pins the channel is connected to.
-				0: VP/VN
-				1: VAUXP[0]/VAUXN[0]
-				2: VAUXP[1]/VAUXN[1]
-				...
-				16: VAUXP[15]/VAUXN[15]
-			  Note each channel number should only be used at most
-			  once.
-		Optional properties:
-			* xlnx,bipolar: If set the channel is used in bipolar
-			  mode.
-
-
-Examples:
-	xadc@f8007100 {
-		compatible = "xlnx,zynq-xadc-1.00.a";
-		reg = <0xf8007100 0x20>;
-		interrupts = <0 7 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&pcap_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-			};
-			channel@1 {
-				reg = <1>;
-			};
-			channel@8 {
-				reg = <8>;
-			};
-		};
-	};
-
-	xadc@43200000 {
-		compatible = "xlnx,axi-xadc-1.00.a";
-		reg = <0x43200000 0x1000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
-
-	adc@80000000 {
-		compatible = "xlnx,system-management-wiz-1.3";
-		reg = <0x80000000 0x1000>;
-		interrupts = <0 81 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
new file mode 100644
index 000000000000..ab6f16109aeb
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XADC and UltraScale System Monitor
+
+maintainers:
+  - Lars-Peter Clausen <lars@metafoo.de>
+
+description: |
+  The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP
+  (Dynamic Reconfiguration Port) interface for communication. Two different
+  frontends for the DRP interface are supported:
+
+    - ZYNQ hardmacro: available only on the ZYNQ family as a hardmacro in
+      the SoC portion of the ZYNQ device.
+    - AXI softmacro: available on all Series 7 platforms as a softmacro
+      with an AXI interface (PG019).
+
+  The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+
+  FPGAs. It is accessed through the Xilinx System Management Wizard IP core
+  via an AXI interface in the FPGA fabric.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,zynq-xadc-1.00.a
+      - xlnx,axi-xadc-1.00.a
+      - xlnx,system-management-wiz-1.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      When using the ZYNQ this must be the ZYNQ PCAP clock.
+      When using the axi-xadc or system-management-wiz this must be
+      the clock that provides the clock to the AXI bus interface.
+    maxItems: 1
+
+  xlnx,external-mux:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: |
+      Selects the external multiplexer mode.
+    enum:
+      - none
+      - single
+      - dual
+
+  xlnx,external-mux-channel:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Configures which pair of pins is used to sample data in external
+      multiplexer mode. This property is required when the device is
+      configured for external multiplexer mode.
+
+      Valid values for single external multiplexer mode:
+        0: VP/VN
+        1-16: VAUXP[0]/VAUXN[0] through VAUXP[15]/VAUXN[15]
+
+      Valid values for dual external multiplexer mode:
+        1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+        2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+        ...
+        8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+    minimum: 0
+    maximum: 16
+
+patternProperties:
+  "^xlnx,channels$":
+    type: object
+    description:
+      List of external channels connected to the ADC. If this property is
+      absent, no external channels are assumed to be connected.
+
+    properties:
+      '#address-cells':
+        const: 1
+
+      '#size-cells':
+        const: 0
+
+    patternProperties:
+      "^channel@([0-9a-f]|10)$":
+        type: object
+        description:
+          Represents an external channel connected to the ADC.
+
+        properties:
+          reg:
+            description: |
+              Pair of pins the channel is connected to.
+                0: VP/VN
+                1: VAUXP[0]/VAUXN[0]
+                2: VAUXP[1]/VAUXN[1]
+                ...
+                16: VAUXP[15]/VAUXN[15]
+            minimum: 0
+            maximum: 16
+
+          xlnx,bipolar:
+            $ref: /schemas/types.yaml#/definitions/flag
+            type: boolean
+            description:
+              If set, the channel is used in bipolar mode.
+
+        required:
+          - reg
+
+        additionalProperties: false
+
+    required:
+      - '#address-cells'
+      - '#size-cells'
+
+    additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        xlnx,external-mux:
+          enum:
+            - single
+            - dual
+      required:
+        - xlnx,external-mux
+    then:
+      required:
+        - xlnx,external-mux-channel
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    /* ZYNQ hardmacro example */
+    adc@f8007100 {
+        compatible = "xlnx,zynq-xadc-1.00.a";
+        reg = <0xf8007100 0x20>;
+        interrupts = <0 7 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&pcap_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+            };
+            channel@1 {
+                reg = <1>;
+            };
+            channel@8 {
+                reg = <8>;
+            };
+        };
+    };
+
+  - |
+    /* AXI softmacro example */
+    adc@43200000 {
+        compatible = "xlnx,axi-xadc-1.00.a";
+        reg = <0x43200000 0x1000>;
+        interrupts = <0 53 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
+
+  - |
+    /* UltraScale System Management Wizard example */
+    adc@80000000 {
+        compatible = "xlnx,system-management-wiz-1.3";
+        reg = <0x80000000 0x1000>;
+        interrupts = <0 81 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75afd16..9b107057ad8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29226,6 +29226,13 @@ F:	Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
 F:	drivers/watchdog/of_xilinx_wdt.c
 F:	drivers/watchdog/xilinx_wwdt.c
 
+XILINX XADC DRIVER
+M:	Lars-Peter Clausen <lars@metafoo.de>
+L:	linux-iio@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
+F:	drivers/iio/adc/xilinx-xadc*
+
 XILINX XDMA DRIVER
 M:	Lizhi Hou <lizhi.hou@amd.com>
 M:	Brian Xu <brian.xu@amd.com>
-- 
2.52.0

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Jonathan Cameron]

On Sun, 10 May 2026 08:01:36 -0400
Pramod Maurya <pramod.nexgen@gmail.com> wrote:

> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> from the legacy plain-text format to a YAML schema, enabling automated
> validation with dt-schema.
> 
> The new binding covers the same hardware and compatible strings:
>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
> 
> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
Hi Pramod,

Something went wrong with your sending of v3. I have two versions sent
half a day apart and no idea how they are related.

Anyhow one of them got feedback from Rob's bot so I'll assume we are
getting a v4 and wait for that.

Jonathan

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[David Lechner]

On 5/11/26 11:15 AM, Jonathan Cameron wrote:
> On Sun, 10 May 2026 08:01:36 -0400
> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
> 
>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>> from the legacy plain-text format to a YAML schema, enabling automated
>> validation with dt-schema.
>>
>> The new binding covers the same hardware and compatible strings:
>>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>
>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
> Hi Pramod,
> 
> Something went wrong with your sending of v3. I have two versions sent
> half a day apart and no idea how they are related.
> 
> Anyhow one of them got feedback from Rob's bot so I'll assume we are
> getting a v4 and wait for that.
> 
> Jonathan

I think Rob will have to fix the bot to make an exception for the
legacy bindings. This should have been called out in the commit message
as requested in a previous revision.

https://lore.kernel.org/linux-iio/20260220053941.611415-6-sai.krishna.potthuri@amd.com/

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Rob Herring]

On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>
> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
> > On Sun, 10 May 2026 08:01:36 -0400
> > Pramod Maurya <pramod.nexgen@gmail.com> wrote:
> >
> >> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> >> from the legacy plain-text format to a YAML schema, enabling automated
> >> validation with dt-schema.
> >>
> >> The new binding covers the same hardware and compatible strings:
> >>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
> >>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
> >>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
> >>
> >> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
> > Hi Pramod,
> >
> > Something went wrong with your sending of v3. I have two versions sent
> > half a day apart and no idea how they are related.
> >
> > Anyhow one of them got feedback from Rob's bot so I'll assume we are
> > getting a v4 and wait for that.
> >
> > Jonathan
>
> I think Rob will have to fix the bot to make an exception for the
> legacy bindings. This should have been called out in the commit message
> as requested in a previous revision.

The bot is not the problem. It just runs validation. The schemas will
have to either drop this check (comma's in nodenames) or exclude just
this property.


Rob

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[David Lechner]

On 5/12/26 7:14 AM, Rob Herring wrote:
> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>>
>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
>>> On Sun, 10 May 2026 08:01:36 -0400
>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
>>>
>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>>>> from the legacy plain-text format to a YAML schema, enabling automated
>>>> validation with dt-schema.
>>>>
>>>> The new binding covers the same hardware and compatible strings:
>>>>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>>>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>>>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>>>
>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
>>> Hi Pramod,
>>>
>>> Something went wrong with your sending of v3. I have two versions sent
>>> half a day apart and no idea how they are related.
>>>
>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
>>> getting a v4 and wait for that.
>>>
>>> Jonathan
>>
>> I think Rob will have to fix the bot to make an exception for the
>> legacy bindings. This should have been called out in the commit message
>> as requested in a previous revision.
> 
> The bot is not the problem. It just runs validation. The schemas will
> have to either drop this check (comma's in nodenames) or exclude just
> this property.
> 
> 
> Rob

Even though this is an existing text-based schema that has been around
for 12 years with this name already? Changing it could be a breaking
change to existing users. Although there aren't any in any .dts in the
kernel source.

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Michal Simek]

On 5/12/26 15:58, David Lechner wrote:
> On 5/12/26 7:14 AM, Rob Herring wrote:
>> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>>>
>>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
>>>> On Sun, 10 May 2026 08:01:36 -0400
>>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
>>>>
>>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>>>>> from the legacy plain-text format to a YAML schema, enabling automated
>>>>> validation with dt-schema.
>>>>>
>>>>> The new binding covers the same hardware and compatible strings:
>>>>>    - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>>>>    - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>>>>    - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>>>>
>>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
>>>> Hi Pramod,
>>>>
>>>> Something went wrong with your sending of v3. I have two versions sent
>>>> half a day apart and no idea how they are related.
>>>>
>>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
>>>> getting a v4 and wait for that.
>>>>
>>>> Jonathan
>>>
>>> I think Rob will have to fix the bot to make an exception for the
>>> legacy bindings. This should have been called out in the commit message
>>> as requested in a previous revision.
>>
>> The bot is not the problem. It just runs validation. The schemas will
>> have to either drop this check (comma's in nodenames) or exclude just
>> this property.
>>
>>
>> Rob
> 
> Even though this is an existing text-based schema that has been around
> for 12 years with this name already? Changing it could be a breaking
> change to existing users. Although there aren't any in any .dts in the
> kernel source.

Zynq has it described.
arch/arm/boot/dts/xilinx/zynq-7000.dtsi:111:                       compatible = 
"xlnx,zynq-xadc-1.00.a";

And make no sense to describe programmable logic which are that other two.

Thanks,
Michal

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[David Lechner]

On 5/12/26 9:10 AM, Michal Simek wrote:
> 
> 
> On 5/12/26 15:58, David Lechner wrote:
>> On 5/12/26 7:14 AM, Rob Herring wrote:
>>> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>>>>
>>>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
>>>>> On Sun, 10 May 2026 08:01:36 -0400
>>>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
>>>>>
>>>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>>>>>> from the legacy plain-text format to a YAML schema, enabling automated
>>>>>> validation with dt-schema.
>>>>>>
>>>>>> The new binding covers the same hardware and compatible strings:
>>>>>>    - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>>>>>    - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>>>>>    - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>>>>>
>>>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
>>>>> Hi Pramod,
>>>>>
>>>>> Something went wrong with your sending of v3. I have two versions sent
>>>>> half a day apart and no idea how they are related.
>>>>>
>>>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
>>>>> getting a v4 and wait for that.
>>>>>
>>>>> Jonathan
>>>>
>>>> I think Rob will have to fix the bot to make an exception for the
>>>> legacy bindings. This should have been called out in the commit message
>>>> as requested in a previous revision.
>>>
>>> The bot is not the problem. It just runs validation. The schemas will
>>> have to either drop this check (comma's in nodenames) or exclude just
>>> this property.
>>>
>>>
>>> Rob
>>
>> Even though this is an existing text-based schema that has been around
>> for 12 years with this name already? Changing it could be a breaking
>> change to existing users. Although there aren't any in any .dts in the
>> kernel source.
> 
> Zynq has it described.
> arch/arm/boot/dts/xilinx/zynq-7000.dtsi:111:                       compatible = "xlnx,zynq-xadc-1.00.a";
> 
> And make no sense to describe programmable logic which are that other two.
> 
> Thanks,
> Michal

The issue is with the xlnx,channels property name. Searching only shows
this in the driver and in the examples in the bindings .txt file.

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Michal Simek]

On 5/12/26 16:16, David Lechner wrote:
> On 5/12/26 9:10 AM, Michal Simek wrote:
>>
>>
>> On 5/12/26 15:58, David Lechner wrote:
>>> On 5/12/26 7:14 AM, Rob Herring wrote:
>>>> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>>>>>
>>>>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
>>>>>> On Sun, 10 May 2026 08:01:36 -0400
>>>>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
>>>>>>
>>>>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>>>>>>> from the legacy plain-text format to a YAML schema, enabling automated
>>>>>>> validation with dt-schema.
>>>>>>>
>>>>>>> The new binding covers the same hardware and compatible strings:
>>>>>>>     - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>>>>>>     - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>>>>>>     - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>>>>>>
>>>>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
>>>>>> Hi Pramod,
>>>>>>
>>>>>> Something went wrong with your sending of v3. I have two versions sent
>>>>>> half a day apart and no idea how they are related.
>>>>>>
>>>>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
>>>>>> getting a v4 and wait for that.
>>>>>>
>>>>>> Jonathan
>>>>>
>>>>> I think Rob will have to fix the bot to make an exception for the
>>>>> legacy bindings. This should have been called out in the commit message
>>>>> as requested in a previous revision.
>>>>
>>>> The bot is not the problem. It just runs validation. The schemas will
>>>> have to either drop this check (comma's in nodenames) or exclude just
>>>> this property.
>>>>
>>>>
>>>> Rob
>>>
>>> Even though this is an existing text-based schema that has been around
>>> for 12 years with this name already? Changing it could be a breaking
>>> change to existing users. Although there aren't any in any .dts in the
>>> kernel source.
>>
>> Zynq has it described.
>> arch/arm/boot/dts/xilinx/zynq-7000.dtsi:111:                       compatible = "xlnx,zynq-xadc-1.00.a";
>>
>> And make no sense to describe programmable logic which are that other two.
>>
>> Thanks,
>> Michal
> 
> The issue is with the xlnx,channels property name. Searching only shows
> this in the driver and in the examples in the bindings .txt file.

Because it depends on HW design configuration. Different configuration have 
different channels exposed. We are using device tree generator which take 
current design configuration and describe them. zynq-7000.dtsi is generic for 
all boards. I can't remember all details but I wouldn't be surprise if no 
channel is exported on minimal/default designs which are described.

Thanks,
Michal

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[David Lechner]

On 5/12/26 8:58 AM, David Lechner wrote:
> On 5/12/26 7:14 AM, Rob Herring wrote:
>> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>>>
>>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
>>>> On Sun, 10 May 2026 08:01:36 -0400
>>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
>>>>
>>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>>>>> from the legacy plain-text format to a YAML schema, enabling automated
>>>>> validation with dt-schema.
>>>>>
>>>>> The new binding covers the same hardware and compatible strings:
>>>>>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>>>>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>>>>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>>>>
>>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
>>>> Hi Pramod,
>>>>
>>>> Something went wrong with your sending of v3. I have two versions sent
>>>> half a day apart and no idea how they are related.
>>>>
>>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
>>>> getting a v4 and wait for that.
>>>>
>>>> Jonathan
>>>
>>> I think Rob will have to fix the bot to make an exception for the
>>> legacy bindings. This should have been called out in the commit message
>>> as requested in a previous revision.
>>
>> The bot is not the problem. It just runs validation. The schemas will
>> have to either drop this check (comma's in nodenames) or exclude just
>> this property.
>>
>>
>> Rob
> 
> Even though this is an existing text-based schema that has been around
> for 12 years with this name already? Changing it could be a breaking
> change to existing users. Although there aren't any in any .dts in the
> kernel source.

Pramod,

Unless Rob changes his mind, the thing to do would be to use the standard
channels property from adc.yaml when converting the binding instead of
xlnx,channels.

We will also need to add handling in the driver for "channels" while
preserving "xlnx,channels" handling for backwards compatibility.

xlnx,channels will just be undocumented.

And all of this reasoning must be explained in the commit messages.

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Rob Herring]

On Tue, May 12, 2026 at 8:58 AM David Lechner <dlechner@baylibre.com> wrote:
>
> On 5/12/26 7:14 AM, Rob Herring wrote:
> > On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
> >>
> >> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
> >>> On Sun, 10 May 2026 08:01:36 -0400
> >>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
> >>>
> >>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> >>>> from the legacy plain-text format to a YAML schema, enabling automated
> >>>> validation with dt-schema.
> >>>>
> >>>> The new binding covers the same hardware and compatible strings:
> >>>>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
> >>>>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
> >>>>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
> >>>>
> >>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
> >>> Hi Pramod,
> >>>
> >>> Something went wrong with your sending of v3. I have two versions sent
> >>> half a day apart and no idea how they are related.
> >>>
> >>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
> >>> getting a v4 and wait for that.
> >>>
> >>> Jonathan
> >>
> >> I think Rob will have to fix the bot to make an exception for the
> >> legacy bindings. This should have been called out in the commit message
> >> as requested in a previous revision.
> >
> > The bot is not the problem. It just runs validation. The schemas will
> > have to either drop this check (comma's in nodenames) or exclude just
> > this property.
> >
> >
> > Rob
>
> Even though this is an existing text-based schema that has been around
> for 12 years with this name already? Changing it could be a breaking
> change to existing users. Although there aren't any in any .dts in the
> kernel source.

I'm absolutely not suggesting changing the node name.

The common schemas globally disallow commas in nodenames. We can relax
that and allow commas in any nodename. That check is largely from
QCom's amazingly consistent use of 'qcom' prefix in nodenames. We've
finally beat that practice out of them. So maybe it's not needed
anymore.

The other approach is to exclude this nodename and any other we have
to keep. I don't like dtschema having to know about some random name,
but we already have that in a few cases and I don't expect that list
to be too long given this is the first case we've seen.

Rob

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[David Lechner]

On 5/12/26 2:42 PM, Rob Herring wrote:
> On Tue, May 12, 2026 at 8:58 AM David Lechner <dlechner@baylibre.com> wrote:
>>
>> On 5/12/26 7:14 AM, Rob Herring wrote:
>>> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
>>>>
>>>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
>>>>> On Sun, 10 May 2026 08:01:36 -0400
>>>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
>>>>>
>>>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
>>>>>> from the legacy plain-text format to a YAML schema, enabling automated
>>>>>> validation with dt-schema.
>>>>>>
>>>>>> The new binding covers the same hardware and compatible strings:
>>>>>>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>>>>>>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>>>>>>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>>>>>>
>>>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
>>>>> Hi Pramod,
>>>>>
>>>>> Something went wrong with your sending of v3. I have two versions sent
>>>>> half a day apart and no idea how they are related.
>>>>>
>>>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
>>>>> getting a v4 and wait for that.
>>>>>
>>>>> Jonathan
>>>>
>>>> I think Rob will have to fix the bot to make an exception for the
>>>> legacy bindings. This should have been called out in the commit message
>>>> as requested in a previous revision.
>>>
>>> The bot is not the problem. It just runs validation. The schemas will
>>> have to either drop this check (comma's in nodenames) or exclude just
>>> this property.
>>>
>>>
>>> Rob
>>
>> Even though this is an existing text-based schema that has been around
>> for 12 years with this name already? Changing it could be a breaking
>> change to existing users. Although there aren't any in any .dts in the
>> kernel source.
> 
> I'm absolutely not suggesting changing the node name.
> 
> The common schemas globally disallow commas in nodenames. We can relax
> that and allow commas in any nodename. That check is largely from
> QCom's amazingly consistent use of 'qcom' prefix in nodenames. We've
> finally beat that practice out of them. So maybe it's not needed
> anymore.
> 
> The other approach is to exclude this nodename and any other we have
> to keep. I don't like dtschema having to know about some random name,
> but we already have that in a few cases and I don't expect that list
> to be too long given this is the first case we've seen.
> 
> Rob

Got it. So when I said "fix the bot" earlier, I should have said
"fix dtschema". We went through this before with adi,channels, but
I didn't remember exactly what you did.

I created a pull request for dt-schema [1] for this since it was
easier than trying to explain it for someone else to do.

[1]: https://github.com/devicetree-org/dt-schema/pull/195

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Rob Herring]

On Tue, May 12, 2026 at 3:03 PM David Lechner <dlechner@baylibre.com> wrote:
>
> On 5/12/26 2:42 PM, Rob Herring wrote:
> > On Tue, May 12, 2026 at 8:58 AM David Lechner <dlechner@baylibre.com> wrote:
> >>
> >> On 5/12/26 7:14 AM, Rob Herring wrote:
> >>> On Mon, May 11, 2026 at 11:24 AM David Lechner <dlechner@baylibre.com> wrote:
> >>>>
> >>>> On 5/11/26 11:15 AM, Jonathan Cameron wrote:
> >>>>> On Sun, 10 May 2026 08:01:36 -0400
> >>>>> Pramod Maurya <pramod.nexgen@gmail.com> wrote:
> >>>>>
> >>>>>> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> >>>>>> from the legacy plain-text format to a YAML schema, enabling automated
> >>>>>> validation with dt-schema.
> >>>>>>
> >>>>>> The new binding covers the same hardware and compatible strings:
> >>>>>>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
> >>>>>>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
> >>>>>>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
> >>>>>>
> >>>>>> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
> >>>>> Hi Pramod,
> >>>>>
> >>>>> Something went wrong with your sending of v3. I have two versions sent
> >>>>> half a day apart and no idea how they are related.
> >>>>>
> >>>>> Anyhow one of them got feedback from Rob's bot so I'll assume we are
> >>>>> getting a v4 and wait for that.
> >>>>>
> >>>>> Jonathan
> >>>>
> >>>> I think Rob will have to fix the bot to make an exception for the
> >>>> legacy bindings. This should have been called out in the commit message
> >>>> as requested in a previous revision.
> >>>
> >>> The bot is not the problem. It just runs validation. The schemas will
> >>> have to either drop this check (comma's in nodenames) or exclude just
> >>> this property.
> >>>
> >>>
> >>> Rob
> >>
> >> Even though this is an existing text-based schema that has been around
> >> for 12 years with this name already? Changing it could be a breaking
> >> change to existing users. Although there aren't any in any .dts in the
> >> kernel source.
> >
> > I'm absolutely not suggesting changing the node name.
> >
> > The common schemas globally disallow commas in nodenames. We can relax
> > that and allow commas in any nodename. That check is largely from
> > QCom's amazingly consistent use of 'qcom' prefix in nodenames. We've
> > finally beat that practice out of them. So maybe it's not needed
> > anymore.
> >
> > The other approach is to exclude this nodename and any other we have
> > to keep. I don't like dtschema having to know about some random name,
> > but we already have that in a few cases and I don't expect that list
> > to be too long given this is the first case we've seen.
> >
> > Rob
>
> Got it. So when I said "fix the bot" earlier, I should have said
> "fix dtschema". We went through this before with adi,channels, but
> I didn't remember exactly what you did.

Completely forgot that. That makes picking which one easy...

> I created a pull request for dt-schema [1] for this since it was
> easier than trying to explain it for someone else to do.
>
> [1]: https://github.com/devicetree-org/dt-schema/pull/195

Thank you! Applied.

Rob

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Jonathan Cameron]

On Sun, 10 May 2026 08:01:36 -0400
Pramod Maurya <pramod.nexgen@gmail.com> wrote:

> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> from the legacy plain-text format to a YAML schema, enabling automated
> validation with dt-schema.
> 
> The new binding covers the same hardware and compatible strings:
>   - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
>   - xlnx,axi-xadc-1.00.a  (AXI softmacro)
>   - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
> 
> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
On another note - please slow down.  I now see that v1-3 all came in less
than 2 days.   Typically wait around a week for a significant patch like
this - that gives time for multiple reviewers to take a look.

Maybe we can relax that given the v3 many versions confusion - but I would
still wait a day or so before sending a v4

Thanks,

Jonathan

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Low] Invalid scalar constraints and missing length bounds on the `reg` property inside channel nodes.
- [Low] Fixed-string property `^xlnx,channels$` is defined in `patternProperties` instead of `properties`.
- [Low] Redundant `type: boolean` declaration for the `xlnx,bipolar` property.
--

commit eb30bdd7a415cc66765c82f5a5300f2adb66fb3c
Author: Pramod Maurya <pramod.nexgen@gmail.com>

dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

This commit converts the Xilinx XADC and UltraScale System Monitor device
tree bindings from the legacy plain-text format to a YAML schema. The new
schema covers the same hardware and compatible strings while enabling
automated validation with dt-schema.

> diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
> new file mode 100644
> index 0000000000000..ab6f16109aebd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
[ ... ]
> +patternProperties:
> +  "^xlnx,channels$":

Is it intentional to place "^xlnx,channels$" in patternProperties? Since this
is a fixed string without any variable or wildcard components, defining it
under patternProperties bypasses explicit property tracking in dt-schema and
usually triggers a dt_binding_check linter warning. Should this be placed in
the properties block instead?

> +    type: object
> +    description:
> +      List of external channels connected to the ADC. If this property is
> +      absent, no external channels are assumed to be connected.
[ ... ]
> +    patternProperties:
> +      "^channel@([0-9a-f]|10)$":
> +        type: object
> +        description:
> +          Represents an external channel connected to the ADC.
> +
> +        properties:
> +          reg:
> +            description: |
> +              Pair of pins the channel is connected to.
> +                0: VP/VN
> +                1: VAUXP[0]/VAUXN[0]
> +                2: VAUXP[1]/VAUXN[1]
> +                ...
> +                16: VAUXP[15]/VAUXN[15]
> +            minimum: 0
> +            maximum: 16

Will this fail dt_binding_check validation? The reg property is intrinsically
an array type in device tree schemas. Applying scalar JSON schema validation
keywords like minimum and maximum directly to an array type is invalid.

Since the node name regex ^channel@([0-9a-f]|10)$ already enforces bounds on
the unit address, should the scalar bounds be removed and replaced with
maxItems: 1?

> +
> +          xlnx,bipolar:
> +            $ref: /schemas/types.yaml#/definitions/flag
> +            type: boolean

This isn't a bug, but the type: boolean declaration here appears redundant.
The reference to /schemas/types.yaml#/definitions/flag intrinsically defines
the node as a boolean-typed property without a value. Can the type: boolean
line be removed to align with standard dt-schema linting rules?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260510120141.118057-1-pramod.nexgen@gmail.com?part=1

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Invalid use of 'minimum' and 'maximum' directly on the 'reg' array property within the 'channel@...' subnode.
--

commit 1ceb6107e206dae61695383d0449f5edc509e233
Author: Pramod Maurya <pramod.nexgen@gmail.com>

dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

This commit converts the legacy plain-text device tree bindings for the
Xilinx XADC and UltraScale System Monitor to the YAML schema format to
enable automated validation.

> diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
[ ... ]
> +    patternProperties:
> +      "^channel@([0-9a-f]|10)$":
> +        type: object
> +        description:
> +          Represents an external channel connected to the ADC.
> +
> +        properties:
> +          reg:
> +            description: |
> +              Pair of pins the channel is connected to.
> +                0: VP/VN
> +                1: VAUXP[0]/VAUXN[0]
> +                2: VAUXP[1]/VAUXN[1]
> +                ...
> +                16: VAUXP[15]/VAUXN[15]
> +            minimum: 0
> +            maximum: 16

Are these minimum and maximum constraints taking effect as intended?

In dt-schema, the reg property is inherently typed as an array. According to
the JSON schema specification, the minimum and maximum validation keywords
apply only to numeric instances and are silently ignored when applied directly
to an array. Because of this, the intended limits on the channel values might
be bypassed during dtbs_check.

Could this be updated to specify maxItems: 1 and apply the numeric limits
inside an items constraint to ensure the correct unit address values are
strictly enforced?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260510083219.70224-1-pramod.nexgen@gmail.com?part=1

[PATCH v4 0/3] Convert Xilinx XADC binding to YAML and related cleanups

[Pramod Maurya]

This series converts the Xilinx XADC device tree binding from the legacy
plain-text format to a validated YAML schema, fixes a checkpatch alignment
warning in the axis-fifo staging driver, and adds a YAML DT binding for
the Xilinx AXI-Stream FIFO IP core.

Patch 1 is v4 of the XADC binding conversion. Previous versions had the
following issues that are now addressed:
  - v3: xlnx,channels was placed in patternProperties to satisfy the
    vendor-props.yaml meta-schema; dt-schema PR#195 (merged by Rob
    Herring) now allows commas in nodenames so it correctly lives in
    properties. A companion dt-schema update is needed to add
    xlnx,channels to the vendor-props.yaml explicit object exceptions
    (similar to the existing adi,channels entry).
  - v3: reg constraints inside channel subnodes used bare minimum/maximum
    keywords which are silently ignored on array types; the description
    now documents the valid range and reg uses maxItems: 1 per cell.yaml.
  - v3: xlnx,bipolar had a redundant type: boolean alongside the $ref
    to /schemas/types.yaml#/definitions/flag; the $ref already implies
    the boolean type so type: boolean is removed.

Patches 2 and 3 are new additions to this series.

Pramod Maurya (3):
  dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema
  staging: axis-fifo: Fix alignment of wait_event_interruptible
    arguments
  dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

 .../bindings/iio/adc/xilinx-xadc.txt          | 141 ------------
 .../bindings/iio/adc/xlnx,xadc.yaml           | 210 ++++++++++++++++++
 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     |  93 ++++++++
 MAINTAINERS                                   |  13 ++
 drivers/staging/axis-fifo/axis-fifo.c         |   3 +-
 5 files changed, 318 insertions(+), 142 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
 create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

-- 
2.52.0

[PATCH v4 1/3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[Pramod Maurya]

Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML schema, enabling automated
validation with dt-schema.

The new binding covers the same hardware and compatible strings:
  - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
  - xlnx,axi-xadc-1.00.a  (AXI softmacro)
  - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)

The xlnx,channels subnode retains its legacy name (including the comma)
for backwards compatibility with existing device trees.

Place xlnx,channels under properties: now that dt-schema PR#195 allows
comma-containing nodenames for long-established bindings. Fix reg
constraints inside channel subnodes to use maxItems and an items block
rather than bare minimum/maximum keywords which are silently ignored on
array types. Remove the redundant type: boolean from xlnx,bipolar since
the $ref to /schemas/types.yaml#/definitions/flag already implies it.

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
Changes in v4:
- Move xlnx,channels from patternProperties: to properties: per Rob
  Herring's guidance (keywords.yaml: "Fixed strings belong in properties")
  This requires a companion dt-schema update to add xlnx,channels as an
  object-type exception in vendor-props.yaml (like adi,channels).
- Fix reg constraints inside channel subnodes: remove items block with
  minimum/maximum which is invalid for cell arrays per cell.yaml; the
  valid channel range (0-16) is documented in the description instead.
- Remove redundant type: boolean from xlnx,bipolar; the $ref to
  /schemas/types.yaml#/definitions/flag already implies boolean type.
- Fix patternProperties regex for channel subnodes to "^channel@([0-9a-f]|10)$"
  covering all valid hex unit addresses for channels 0-16.

Changes in v3:
- Move xlnx,channels from properties: to patternProperties: to satisfy
  vendor-props.yaml meta-schema (reversed in v4, see above)

Changes in v2:
- Fix patternProperties regex to use lowercase hex unit addresses
- Add allOf/if/then conditional requiring xlnx,external-mux-channel
  when xlnx,external-mux is "single" or "dual"

 .../bindings/iio/adc/xilinx-xadc.txt          | 141 ------------
 .../bindings/iio/adc/xlnx,xadc.yaml           | 210 ++++++++++++++++++
 MAINTAINERS                                   |   7 +
 3 files changed, 217 insertions(+), 141 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
 create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml

diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
-	- compatible: Should be one of
-		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
-		  configuration interface to interface to the XADC hardmacro.
-		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
-		  interface to the XADC hardmacro.
-		* "xlnx,system-management-wiz-1.3": When using the
-		  Xilinx System Management Wizard fabric IP core to access the
-		  UltraScale and UltraScale+ System Monitor.
-	- reg: Address and length of the register set for the device
-	- interrupts: Interrupt for the XADC control interface.
-	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
-	  when using the axi-xadc or the axi-system-management-wizard this must be
-	  the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
-	- xlnx,external-mux:
-		* "none": No external multiplexer is used, this is the default
-		  if the property is omitted.
-		* "single": External multiplexer mode is used with one
-		   multiplexer.
-		* "dual": External multiplexer mode is used with two
-		  multiplexers for simultaneous sampling.
-	- xlnx,external-mux-channel: Configures which pair of pins is used to
-	  sample data in external mux mode.
-	  Valid values for single external multiplexer mode are:
-		0: VP/VN
-		1: VAUXP[0]/VAUXN[0]
-		2: VAUXP[1]/VAUXN[1]
-		...
-		16: VAUXP[15]/VAUXN[15]
-	  Valid values for dual external multiplexer mode are:
-		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
-		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
-		...
-		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
-	  This property needs to be present if the device is configured for
-	  external multiplexer mode (either single or dual). If the device is
-	  not using external multiplexer mode the property is ignored.
-	- xnlx,channels: List of external channels that are connected to the ADC
-	  Required properties:
-		* #address-cells: Should be 1.
-		* #size-cells: Should be 0.
-
-	  The child nodes of this node represent the external channels which are
-	  connected to the ADC. If the property is no present no external
-	  channels will be assumed to be connected.
-
-	  Each child node represents one channel and has the following
-	  properties:
-		Required properties:
-			* reg: Pair of pins the channel is connected to.
-				0: VP/VN
-				1: VAUXP[0]/VAUXN[0]
-				2: VAUXP[1]/VAUXN[1]
-				...
-				16: VAUXP[15]/VAUXN[15]
-			  Note each channel number should only be used at most
-			  once.
-		Optional properties:
-			* xlnx,bipolar: If set the channel is used in bipolar
-			  mode.
-
-
-Examples:
-	xadc@f8007100 {
-		compatible = "xlnx,zynq-xadc-1.00.a";
-		reg = <0xf8007100 0x20>;
-		interrupts = <0 7 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&pcap_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-			};
-			channel@1 {
-				reg = <1>;
-			};
-			channel@8 {
-				reg = <8>;
-			};
-		};
-	};
-
-	xadc@43200000 {
-		compatible = "xlnx,axi-xadc-1.00.a";
-		reg = <0x43200000 0x1000>;
-		interrupts = <0 53 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
-
-	adc@80000000 {
-		compatible = "xlnx,system-management-wiz-1.3";
-		reg = <0x80000000 0x1000>;
-		interrupts = <0 81 4>;
-		interrupt-parent = <&gic>;
-		clocks = <&fpga1_clk>;
-
-		xlnx,channels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-				xlnx,bipolar;
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
new file mode 100644
index 000000000000..06a0ce498352
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XADC and UltraScale System Monitor
+
+maintainers:
+  - Lars-Peter Clausen <lars@metafoo.de>
+
+description: |
+  The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP
+  (Dynamic Reconfiguration Port) interface for communication. Two different
+  frontends for the DRP interface are supported:
+
+    - ZYNQ hardmacro: available only on the ZYNQ family as a hardmacro in
+      the SoC portion of the ZYNQ device.
+    - AXI softmacro: available on all Series 7 platforms as a softmacro
+      with an AXI interface (PG019).
+
+  The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+
+  FPGAs. It is accessed through the Xilinx System Management Wizard IP core
+  via an AXI interface in the FPGA fabric.
+
+  The xlnx,channels subnode name contains a comma as part of the legacy
+  device tree binding that has been in use for over a decade. This name is
+  retained for backwards compatibility with existing device trees.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,zynq-xadc-1.00.a
+      - xlnx,axi-xadc-1.00.a
+      - xlnx,system-management-wiz-1.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      When using the ZYNQ this must be the ZYNQ PCAP clock.
+      When using the axi-xadc or system-management-wiz this must be
+      the clock that provides the clock to the AXI bus interface.
+    maxItems: 1
+
+  xlnx,external-mux:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: |
+      Selects the external multiplexer mode. If omitted, no external
+      multiplexer is used.
+    enum:
+      - none
+      - single
+      - dual
+
+  xlnx,external-mux-channel:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Configures which pair of pins is used to sample data in external
+      multiplexer mode. Required when xlnx,external-mux is "single" or
+      "dual".
+
+      Valid values for single external multiplexer mode:
+        0: VP/VN
+        1: VAUXP[0]/VAUXN[0]
+        2: VAUXP[1]/VAUXN[1]
+        ...
+        16: VAUXP[15]/VAUXN[15]
+
+      Valid values for dual external multiplexer mode:
+        1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+        2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+        ...
+        8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+    minimum: 0
+    maximum: 16
+
+  xlnx,channels:
+    type: object
+    description:
+      List of external channels connected to the ADC. If this node is
+      absent, no external channels are assumed to be connected.
+
+    properties:
+      '#address-cells':
+        const: 1
+
+      '#size-cells':
+        const: 0
+
+    patternProperties:
+      "^channel@([0-9a-f]|10)$":
+        type: object
+        description:
+          Represents an external channel connected to the ADC.
+
+        properties:
+          reg:
+            description: |
+              Pair of pins the channel is connected to.
+                0: VP/VN
+                1: VAUXP[0]/VAUXN[0]
+                2: VAUXP[1]/VAUXN[1]
+                ...
+                16: VAUXP[15]/VAUXN[15]
+            maxItems: 1
+
+          xlnx,bipolar:
+            $ref: /schemas/types.yaml#/definitions/flag
+            description:
+              If set, the channel is used in bipolar mode.
+
+        required:
+          - reg
+
+        additionalProperties: false
+
+    required:
+      - '#address-cells'
+      - '#size-cells'
+
+    additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        xlnx,external-mux:
+          enum:
+            - single
+            - dual
+      required:
+        - xlnx,external-mux
+    then:
+      required:
+        - xlnx,external-mux-channel
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    /* ZYNQ hardmacro example */
+    adc@f8007100 {
+        compatible = "xlnx,zynq-xadc-1.00.a";
+        reg = <0xf8007100 0x20>;
+        interrupts = <0 7 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&pcap_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+            };
+            channel@1 {
+                reg = <1>;
+            };
+            channel@8 {
+                reg = <8>;
+            };
+        };
+    };
+
+  - |
+    /* AXI softmacro example */
+    adc@43200000 {
+        compatible = "xlnx,axi-xadc-1.00.a";
+        reg = <0x43200000 0x1000>;
+        interrupts = <0 53 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
+
+  - |
+    /* UltraScale System Management Wizard example */
+    adc@80000000 {
+        compatible = "xlnx,system-management-wiz-1.3";
+        reg = <0x80000000 0x1000>;
+        interrupts = <0 81 4>;
+        interrupt-parent = <&gic>;
+        clocks = <&fpga1_clk>;
+
+        xlnx,channels {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            channel@0 {
+                reg = <0>;
+                xlnx,bipolar;
+            };
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index b2040011a386..58d35c17704d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29266,6 +29266,13 @@ F:	Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
 F:	drivers/watchdog/of_xilinx_wdt.c
 F:	drivers/watchdog/xilinx_wwdt.c
 
+XILINX XADC DRIVER
+M:	Lars-Peter Clausen <lars@metafoo.de>
+L:	linux-iio@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
+F:	drivers/iio/adc/xilinx-xadc*
+
 XILINX XDMA DRIVER
 M:	Lizhi Hou <lizhi.hou@amd.com>
 M:	Brian Xu <brian.xu@amd.com>
-- 
2.52.0

Re: [PATCH v4 1/3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The channel subnode 'reg' property is missing the 'items' constraint block to restrict the valid channel numbers, contradicting the commit message.
--

commit fd4f54c07b6e4f122c96ac428cd51a740a0e5ca2
Author: Pramod Maurya <pramod.nexgen@gmail.com>

dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML schema, enabling automated
validation with dt-schema.

> diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
> new file mode 100644
> index 0000000000000..06a0ce4983523
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
[ ... ]
> +    patternProperties:
> +      "^channel@([0-9a-f]|10)$":
> +        type: object
> +        description:
> +          Represents an external channel connected to the ADC.
> +
> +        properties:
> +          reg:
> +            description: |
> +              Pair of pins the channel is connected to.
> +                0: VP/VN
> +                1: VAUXP[0]/VAUXN[0]
> +                2: VAUXP[1]/VAUXN[1]
> +                ...
> +                16: VAUXP[15]/VAUXN[15]
> +            maxItems: 1

The commit message states: "Fix reg constraints inside channel subnodes to use
maxItems and an items block rather than bare minimum/maximum keywords which
are silently ignored on array types."

Is the items block missing from this property? Without an items constraint
defining the minimum and maximum limits, the schema might accept invalid
out-of-range hardware pin mappings. Could an items block be included here to
enforce the 0 to 16 limits?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515075736.172172-1-pramod.nexgen@gmail.com?part=1

[PATCH v4 2/3] staging: axis-fifo: Fix alignment of wait_event_interruptible arguments

[Pramod Maurya]

The second argument to wait_event_interruptible() was indented with a
single tab instead of being aligned to the opening parenthesis. Since
the fully-aligned form exceeds 80 columns, break the condition at the
comparison operator and align the continuation line to the opening
parenthesis.

Fixes the following checkpatch.pl warning:
  CHECK: Alignment should match open parenthesis

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
 drivers/staging/axis-fifo/axis-fifo.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c
index 3aa2aa870ea9..1c34de020cf8 100644
--- a/drivers/staging/axis-fifo/axis-fifo.c
+++ b/drivers/staging/axis-fifo/axis-fifo.c
@@ -246,7 +246,8 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
 		mutex_lock(&fifo->write_lock);
 
 		ret = wait_event_interruptible(fifo->write_queue,
-			ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >= words_to_write);
+					       ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >=
+					       words_to_write);
 		if (ret)
 			goto end_unlock;
 	}
-- 
2.52.0

Re: [PATCH v4 2/3] staging: axis-fifo: Fix alignment of wait_event_interruptible arguments

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The driver incorrectly uses register I/O accessors (iowrite32/ioread32) for FIFO stream data, corrupting the payload byte order on big-endian architectures.
--

commit 2b61bbc0527fc4d755d68d7a70237195d89efad6
Author: Pramod Maurya <pramod.nexgen@gmail.com>

staging: axis-fifo: Fix alignment of wait_event_interruptible arguments

This commit resolves a checkpatch warning about argument alignment in
wait_event_interruptible(). It breaks the condition at the comparison
operator to keep the line under 80 columns.

> diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c
> index 3aa2aa870ea91..1c34de020cf85 100644
> --- a/drivers/staging/axis-fifo/axis-fifo.c
> +++ b/drivers/staging/axis-fifo/axis-fifo.c
> @@ -246,7 +246,8 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
>  		mutex_lock(&fifo->write_lock);
>  
>  		ret = wait_event_interruptible(fifo->write_queue,
> -			ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >= words_to_write);
> +					       ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >=
> +					       words_to_write);
>  		if (ret)
>  			goto end_unlock;
>  	}

This isn't a bug introduced by this commit, but while reviewing
axis_fifo_write() I noticed a potential endianness issue later in the
function:

	for (int i = 0; i < words_to_write; ++i)
		iowrite32(txbuf[i], fifo->base_addr + XLLF_TDFD_OFFSET);

Could this loop corrupt the payload byte order on big-endian architectures?

Stream data fifos must exclusively use stream accessors (such as writesl()
and readsl()) to preserve memory byte order without applying unwanted
byte-swapping.

The driver currently uses register I/O accessors to transfer data to and
from the fifos (XLLF_TDFD_OFFSET and XLLF_RDFD_OFFSET). On big-endian
systems, iowrite32() maps to writel(), which performs CPU-to-device
byteswapping.

Are there similar issues in axis_fifo_read() where ioread32() is used to
read from XLLF_RDFD_OFFSET?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515075736.172172-1-pramod.nexgen@gmail.com?part=2

[PATCH v4 3/3] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[Pramod Maurya]

Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080).
The binding documents the three supported compatible strings and the
vendor-specific properties that the axis-fifo staging driver reads from
the device tree.

This resolves the following checkpatch.pl warnings in
drivers/staging/axis-fifo/axis-fifo.c:
  WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
  WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
  WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documented

Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 93 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++
 2 files changed, 99 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
new file mode 100644
index 000000000000..f4ef7c277cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AXI-Stream FIFO
+
+maintainers:
+  - Jacob Feder <jacobsfeder@gmail.com>
+
+description:
+  The Xilinx AXI-Stream FIFO (PG080) provides a memory-mapped interface to
+  an AXI-Stream FIFO IP core. It allows a processor to transmit and receive
+  AXI-Stream packets via simple MMIO register reads and writes. Currently
+  only store-forward mode with a 32-bit AXI4-Lite interface is supported.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,axi-fifo-mm-s-4.1
+      - xlnx,axi-fifo-mm-s-4.2
+      - xlnx,axi-fifo-mm-s-4.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  xlnx,axi-str-rxd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Width of the receive AXI-Stream data bus in bits. Currently only 32
+      is supported.
+    const: 32
+
+  xlnx,axi-str-txd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Width of the transmit AXI-Stream data bus in bits. Currently only 32
+      is supported.
+    const: 32
+
+  xlnx,rx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of the receive FIFO in words.
+
+  xlnx,tx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of the transmit FIFO in words.
+
+  xlnx,use-rx-data:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Set to 1 if the receive data FIFO is enabled, 0 otherwise.
+    enum: [0, 1]
+
+  xlnx,use-tx-data:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Set to 1 if the transmit data FIFO is enabled, 0 otherwise.
+    enum: [0, 1]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - xlnx,axi-str-rxd-tdata-width
+  - xlnx,axi-str-txd-tdata-width
+  - xlnx,rx-fifo-depth
+  - xlnx,tx-fifo-depth
+  - xlnx,use-rx-data
+  - xlnx,use-tx-data
+
+additionalProperties: false
+
+examples:
+  - |
+    axi_fifo: fifo@43c00000 {
+        compatible = "xlnx,axi-fifo-mm-s-4.3";
+        reg = <0x43c00000 0x10000>;
+        interrupts = <0 30 4>;
+        interrupt-parent = <&intc>;
+        xlnx,axi-str-rxd-tdata-width = <32>;
+        xlnx,axi-str-txd-tdata-width = <32>;
+        xlnx,rx-fifo-depth = <0x1000>;
+        xlnx,tx-fifo-depth = <0x1000>;
+        xlnx,use-rx-data = <1>;
+        xlnx,use-tx-data = <1>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 58d35c17704d..bbb6b8c20ed6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29164,6 +29164,12 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
 F:	drivers/iio/adc/xilinx-ams.c
 
+XILINX AXI-STREAM FIFO DRIVER
+M:	Jacob Feder <jacobsfeder@gmail.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
+F:	drivers/staging/axis-fifo/
+
 XILINX AXI ETHERNET DRIVER
 M:	Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
 S:	Maintained
-- 
2.52.0

Re: [PATCH v4 3/3] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The YAML schema incorrectly rejects valid hardware device trees by defining software driver limits instead of hardware IP properties and using `additionalProperties: false`.
- [High] The axis-fifo driver incorrectly uses register I/O accessors for stream FIFOs, causing data corruption on big-endian architectures.
- [Medium] Stale text binding documentation is not removed.
--

commit 26ea5f81e17b89c4409b6dcc57391cb51c42f3f2
Author: Pramod Maurya <pramod.nexgen@gmail.com>

dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

This patch adds a YAML schema for the Xilinx AXI-Stream FIFO IP core to
resolve checkpatch warnings about undocumented compatible strings.

>     The binding documents the three supported compatible strings and the
>     vendor-specific properties that the axis-fifo staging driver reads from
>     the device tree.

Device tree bindings are generally meant to describe the hardware IP rather
than only what a specific software driver currently uses. By only including
properties the driver reads, are we missing fundamental hardware properties?

Also, since this introduces a formal YAML binding for these compatible
strings, should this patch also remove the obsolete text binding at
drivers/staging/axis-fifo/axis-fifo.txt to prevent conflicting documentation?

>     This resolves the following checkpatch.pl warnings in
>     drivers/staging/axis-fifo/axis-fifo.c:

While not introduced by this patch, the axis-fifo driver mentioned here
appears to use ioread32() and iowrite32() in loops for bulk data transfers
to the FIFO data registers.

Since register accessors perform implicit CPU-to-device byteswapping on
big-endian architectures, does this cause silent data corruption of the byte
stream? Would it be safer to use stream accessors like ioread32_rep() or
readsl() for the FIFO data transfers?

> diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> new file mode 100644
> index 0000000000000..f4ef7c277cd7a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

[ ... ]

> +  xlnx,axi-str-rxd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Width of the receive AXI-Stream data bus in bits. Currently only 32
> +      is supported.
> +    const: 32

Is it appropriate to encode a temporary software driver limitation into the
permanent schema? By strictly constraining this to 32, does this artificially
reject valid hardware device trees that correctly model an IP configured with
a different data width?

> +
> +  xlnx,axi-str-txd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Width of the transmit AXI-Stream data bus in bits. Currently only 32
> +      is supported.
> +    const: 32

Similar to the above, does this const constraint improperly embed a driver
limitation into the hardware binding?

[ ... ]

> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - xlnx,axi-str-rxd-tdata-width
> +  - xlnx,axi-str-txd-tdata-width
> +  - xlnx,rx-fifo-depth
> +  - xlnx,tx-fifo-depth
> +  - xlnx,use-rx-data
> +  - xlnx,use-tx-data
> +
> +additionalProperties: false

Since this sets additionalProperties to false but omits properties like
clocks (required for any synchronous AXI block), interrupt-names, and other
properties that were documented in the previous text binding, will valid
hardware device trees falsely fail dt_binding_check validation?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515075736.172172-1-pramod.nexgen@gmail.com?part=3

Re: [PATCH v4 3/3] dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO

[Krzysztof Kozlowski]

On Fri, May 15, 2026 at 03:57:36AM -0400, Pramod Maurya wrote:
> Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080).
> The binding documents the three supported compatible strings and the
> vendor-specific properties that the axis-fifo staging driver reads from
> the device tree.
> 
> This resolves the following checkpatch.pl warnings in
> drivers/staging/axis-fifo/axis-fifo.c:
>   WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
>   WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
>   WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documented

Do not fix checkpatch warnings blindly. You could have checked the
mailing list before sending this.

Best regards,
Krzysztof

Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20260510083219.70224-1-pramod.nexgen@gmail.com>
References: <20260510083219.70224-1-pramod.nexgen@gmail.com>
TO: Pramod Maurya <pramod.nexgen@gmail.com>
TO: jic23@kernel.org
CC: pramod.nexgen@gmail.com
CC: David Lechner <dlechner@baylibre.com>
CC: "Nuno Sá" <nuno.sa@analog.com>
CC: Andy Shevchenko <andy@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk@kernel.org>
CC: Conor Dooley <conor+dt@kernel.org>
CC: Michal Simek <monstr@monstr.eu>
CC: "Lars-Peter Clausen" <lars@metafoo.de>
CC: linux-iio@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-kernel@vger.kernel.org

Hi Pramod,

kernel test robot noticed the following build warnings:

[auto build test WARNING on jic23-iio/togreg]
[also build test WARNING on robh/for-next linus/master v6.16-rc1 next-20260508]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Pramod-Maurya/dt-bindings-iio-adc-Convert-xilinx-xadc-bindings-to-YAML-schema/20260512-144359
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link:    https://lore.kernel.org/r/20260510083219.70224-1-pramod.nexgen%40gmail.com
patch subject: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema
:::::: branch date: 10 hours ago
:::::: commit date: 10 hours ago
config: arc-randconfig-2051-20260512 (https://download.01.org/0day-ci/archive/20260512/202605121802.IfwQN2uI-lkp@intel.com/config)
compiler: arc-linux-gcc (GCC) 10.5.0
dtschema: 2026.5.dev4+g4ccc1997d
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260512/202605121802.IfwQN2uI-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202605121802.IfwQN2uI-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml: patternProperties: '^xlnx,channels$' should not be valid under {'pattern': '^\\^[a-zA-Z0-9,\\-._#@]+\\$$'}
   	hint: Fixed strings belong in 'properties', not 'patternProperties'
   	from schema $id: http://devicetree.org/meta-schemas/keywords.yaml

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki