From: Ewan Hai <ewandevelop@gmail.com>
To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org,
mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
x86@kernel.org, hpa@zytor.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: cobechen@zhaoxin.com, tonywwang@zhaoxin.com
Subject: [PATCH 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature
Date: Wed, 13 May 2026 17:36:29 +0800 [thread overview]
Message-ID: <20260513093633.1608334-2-ewandevelop@gmail.com> (raw)
In-Reply-To: <20260513093633.1608334-1-ewandevelop@gmail.com>
Advertise the Zhaoxin SM2 instruction support to guests via CPUID
0xC0000001 EDX bits 0 (SM2) and 1 (SM2_EN).
The SM2 instruction (encoding F2 0F A6 C0) implements the SM2
elliptic-curve public-key cryptography algorithm specified in
GM/T 0003-2012; the hardware-level behavior is documented in the
Zhaoxin GMI Instruction Set Reference, chapter 1 ("SM2"). The
instruction multiplexes its sub-functions on the RDX[5:0] control
word: encryption (subsection 1.1), decryption (1.2), signing (1.3),
signature verification (1.4), the three key-exchange sub-operations
of section 1.5 (1.5.1 SM2 key-pair generation, which the spec also
uses for the initiator's ephemeral key; 1.5.2 responder shared-key
derivation; 1.5.3 initiator shared-key derivation), and two
preprocess steps for identity and message hashing (1.6.1 and 1.6.2).
The instruction is user-mode and available in all CPU modes, with no
associated MSR control. The SM2 and SM2_EN bits are redundant by
hardware design (set or cleared together) and both serve purely as
CPUID-level feature-presence reporting flags requiring no KVM
emulation. Both bits are advertised because different software may
probe either one when checking for SM2 availability.
Signed-off-by: Ewan Hai <ewandevelop@gmail.com>
---
arch/x86/kvm/cpuid.c | 2 ++
arch/x86/kvm/reverse_cpuid.h | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e69156b54cff..1eb4b88aaa80 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1272,6 +1272,8 @@ void kvm_initialize_cpu_caps(void)
kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE);
kvm_cpu_cap_init(CPUID_C000_0001_EDX,
+ F(SM2),
+ F(SM2_EN),
F(XSTORE),
F(XSTORE_EN),
F(XCRYPT),
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 657f5f743ed9..7b55110cc046 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -76,6 +76,10 @@
#define KVM_X86_FEATURE_TSA_SQ_NO KVM_X86_FEATURE(CPUID_8000_0021_ECX, 1)
#define KVM_X86_FEATURE_TSA_L1_NO KVM_X86_FEATURE(CPUID_8000_0021_ECX, 2)
+/* Zhaoxin/Centaur sub-features, CPUID level 0xC0000001 (EDX) */
+#define X86_FEATURE_SM2 KVM_X86_FEATURE(CPUID_C000_0001_EDX, 0)
+#define X86_FEATURE_SM2_EN KVM_X86_FEATURE(CPUID_C000_0001_EDX, 1)
+
struct cpuid_reg {
u32 function;
u32 index;
--
2.34.1
next prev parent reply other threads:[~2026-05-13 9:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 9:36 [PATCH 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13 9:36 ` Ewan Hai [this message]
2026-05-13 10:36 ` [PATCH 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Binbin Wu
2026-05-14 2:31 ` Ewan Hai
2026-05-14 6:49 ` Binbin Wu
2026-05-14 6:58 ` Ewan Hai
2026-05-13 9:36 ` [PATCH 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) " Ewan Hai
2026-05-13 9:36 ` [PATCH 3/5] KVM: x86: Expose Zhaoxin RNG2 " Ewan Hai
2026-05-13 9:36 ` [PATCH 4/5] KVM: x86: Expose Zhaoxin PHE2 " Ewan Hai
2026-05-13 9:36 ` [PATCH 5/5] KVM: x86: Expose Zhaoxin RSA " Ewan Hai
-- strict thread matches above, loose matches on Subject: below --
2026-05-13 8:30 [PATCH 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13 8:30 ` [PATCH 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Ewan Hai
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