From: Ewan Hai <ewandevelop@gmail.com>
To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org,
mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
x86@kernel.org, hpa@zytor.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: cobechen@zhaoxin.com, tonywwang@zhaoxin.com
Subject: [PATCH 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) CPUID feature
Date: Wed, 13 May 2026 17:36:30 +0800 [thread overview]
Message-ID: <20260513093633.1608334-3-ewandevelop@gmail.com> (raw)
In-Reply-To: <20260513093633.1608334-1-ewandevelop@gmail.com>
Advertise the Zhaoxin CCS (Chinese Cryptography Standard) feature to
guests via CPUID 0xC0000001 EDX bits 4 (CCS) and 5 (CCS_EN). CCS groups
two user-mode instructions for Chinese national cryptographic
primitives, documented in the Zhaoxin GMI Instruction Set Reference,
chapter 2 ("CCS instruction group"):
- SM3 (encoding F3 0F A6 E8, subsection 2.1) implements the SM3 hash
algorithm specified in GM/T 0004-2012. It supports two modes
selected by RAX: auto-padding stream mode (RAX=0) and pre-padded
block mode (RAX=-1).
- SM4 (encoding F3 0F A7 F0, subsection 2.2) implements the SM4 block
cipher specified in GM/T 0002-2012, supporting ECB / CBC / CFB /
OFB / CTR modes via a control word in RAX, and CBC-MAC / CFB-MAC
when RAX bit[11] is set.
Both instructions are user-mode and available in all CPU modes, with no
associated MSR control. The CCS and CCS_EN bits are redundant by
hardware design (set or cleared together) and both serve purely as
CPUID-level feature-presence reporting flags requiring no KVM
emulation. Both bits are advertised because different software may
probe either one when checking for CCS availability.
Signed-off-by: Ewan Hai <ewandevelop@gmail.com>
---
arch/x86/kvm/cpuid.c | 2 ++
arch/x86/kvm/reverse_cpuid.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 1eb4b88aaa80..8aaa3f20670e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1276,6 +1276,8 @@ void kvm_initialize_cpu_caps(void)
F(SM2_EN),
F(XSTORE),
F(XSTORE_EN),
+ F(CCS),
+ F(CCS_EN),
F(XCRYPT),
F(XCRYPT_EN),
F(ACE2),
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 7b55110cc046..a1cd9116ef63 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -79,6 +79,8 @@
/* Zhaoxin/Centaur sub-features, CPUID level 0xC0000001 (EDX) */
#define X86_FEATURE_SM2 KVM_X86_FEATURE(CPUID_C000_0001_EDX, 0)
#define X86_FEATURE_SM2_EN KVM_X86_FEATURE(CPUID_C000_0001_EDX, 1)
+#define X86_FEATURE_CCS KVM_X86_FEATURE(CPUID_C000_0001_EDX, 4)
+#define X86_FEATURE_CCS_EN KVM_X86_FEATURE(CPUID_C000_0001_EDX, 5)
struct cpuid_reg {
u32 function;
--
2.34.1
next prev parent reply other threads:[~2026-05-13 9:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 9:36 [PATCH 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13 9:36 ` [PATCH 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Ewan Hai
2026-05-13 10:36 ` Binbin Wu
2026-05-14 2:31 ` Ewan Hai
2026-05-14 6:49 ` Binbin Wu
2026-05-14 6:58 ` Ewan Hai
2026-05-13 9:36 ` Ewan Hai [this message]
2026-05-13 9:36 ` [PATCH 3/5] KVM: x86: Expose Zhaoxin RNG2 " Ewan Hai
2026-05-13 9:36 ` [PATCH 4/5] KVM: x86: Expose Zhaoxin PHE2 " Ewan Hai
2026-05-13 9:36 ` [PATCH 5/5] KVM: x86: Expose Zhaoxin RSA " Ewan Hai
-- strict thread matches above, loose matches on Subject: below --
2026-05-13 8:30 [PATCH 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13 8:30 ` [PATCH 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) CPUID feature Ewan Hai
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