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From: Ewan Hai <ewandevelop@gmail.com>
To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org,
	mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
	x86@kernel.org, hpa@zytor.com, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: cobechen@zhaoxin.com, tonywwang@zhaoxin.com
Subject: [PATCH 4/5] KVM: x86: Expose Zhaoxin PHE2 CPUID feature
Date: Wed, 13 May 2026 17:36:32 +0800	[thread overview]
Message-ID: <20260513093633.1608334-5-ewandevelop@gmail.com> (raw)
In-Reply-To: <20260513093633.1608334-1-ewandevelop@gmail.com>

Advertise the Zhaoxin PadLock Hash Engine v2 to guests via CPUID
0xC0000001 EDX bits 25 (PHE2) and 26 (PHE2_EN). PHE2 extends the
PadLock hash family with SHA-384 and SHA-512 support per FIPS 180-3,
complementing the existing PHE feature (SHA-1 and SHA-256).

Two user-mode instructions are exposed, documented in the Zhaoxin
PadLock Instruction Reference, chapter 3 ("Hash Engine"):

  - REP XSHA384 (encoding F3 0F A6 D8, subsection 3.3)
  - REP XSHA512 (encoding F3 0F A6 E0, subsection 3.4)

Both consume software-padded 128-byte blocks (RCX = block count, RSI =
input, RDI = state) and produce hash output in the state buffer.

Both instructions are user-mode and available in all CPU modes, with no
associated MSR control. The PHE2 and PHE2_EN bits are redundant by
hardware design (set or cleared together) and both serve purely as
CPUID-level feature-presence reporting flags requiring no KVM
emulation. Both bits are advertised because different software may
probe either one when checking for PHE2 availability.

Signed-off-by: Ewan Hai <ewandevelop@gmail.com>
---
 arch/x86/kvm/cpuid.c         | 2 ++
 arch/x86/kvm/reverse_cpuid.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 087c41341240..3fb81f7a6107 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1288,6 +1288,8 @@ void kvm_initialize_cpu_caps(void)
 		F(PMM_EN),
 		F(RNG2),
 		F(RNG2_EN),
+		F(PHE2),
+		F(PHE2_EN),
 	);
 
 	/*
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 859ba43126d8..f28300c2d5e0 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -83,6 +83,8 @@
 #define X86_FEATURE_CCS_EN		KVM_X86_FEATURE(CPUID_C000_0001_EDX, 5)
 #define X86_FEATURE_RNG2		KVM_X86_FEATURE(CPUID_C000_0001_EDX, 22)
 #define X86_FEATURE_RNG2_EN		KVM_X86_FEATURE(CPUID_C000_0001_EDX, 23)
+#define X86_FEATURE_PHE2		KVM_X86_FEATURE(CPUID_C000_0001_EDX, 25)
+#define X86_FEATURE_PHE2_EN		KVM_X86_FEATURE(CPUID_C000_0001_EDX, 26)
 
 struct cpuid_reg {
 	u32 function;
-- 
2.34.1


  parent reply	other threads:[~2026-05-13  9:36 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-13  9:36 [PATCH 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13  9:36 ` [PATCH 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Ewan Hai
2026-05-13 10:36   ` Binbin Wu
2026-05-14  2:31     ` Ewan Hai
2026-05-14  6:49       ` Binbin Wu
2026-05-14  6:58         ` Ewan Hai
2026-05-13  9:36 ` [PATCH 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) " Ewan Hai
2026-05-13  9:36 ` [PATCH 3/5] KVM: x86: Expose Zhaoxin RNG2 " Ewan Hai
2026-05-13  9:36 ` Ewan Hai [this message]
2026-05-13  9:36 ` [PATCH 5/5] KVM: x86: Expose Zhaoxin RSA " Ewan Hai
  -- strict thread matches above, loose matches on Subject: below --
2026-05-13  8:30 [PATCH 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-13  8:30 ` [PATCH 4/5] KVM: x86: Expose Zhaoxin PHE2 CPUID feature Ewan Hai

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