From: Eric Auger <eric.auger@redhat.com>
To: eric.auger.pro@gmail.com, eric.auger@redhat.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
kvmarm@lists.linux.dev, peter.maydell@linaro.org,
shaju.abraham@nutanix.com, khushit.shah@nutanix.com,
yangjinqian1@huawei.com, cohuck@redhat.com,
richard.henderson@linaro.org, sebott@redhat.com,
skolothumtho@nvidia.com, philmd@linaro.org
Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,
armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,
jdenemar@redhat.com
Subject: [PATCH v5 12/18] arm/kvm: write back modified ID regs to KVM
Date: Tue, 19 May 2026 15:27:26 +0200 [thread overview]
Message-ID: <20260519132905.145643-13-eric.auger@redhat.com> (raw)
In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com>
In case some ID reg values were overriden after their
initialization in kvm_arm_get_host_cpu_features() we need to
copy the new value stored in isar.idregs array back to the
cpreg_list and then sync the cpreg_list to KVM.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
v4 -> v5:
- only call kvm_arm_writable_idregs_to_cpreg_list and
write_list_to_kvmstate if writable_map is allocated
- reinitialize the cpreg list after sync (Jinqian)
---
target/arm/kvm.c | 69 ++++++++++++++++++++++++++++++++++++++++-
target/arm/trace-events | 1 +
2 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 92219ee62e..30c5175c68 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -274,6 +274,21 @@ static uint32_t kvm_arm_sve_get_vls(int fd)
return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ);
}
+static int kvm_feature_idx_to_idregs_idx(int kidx)
+{
+ int op1, crm, op2;
+ ARMSysRegs sysreg;
+
+ op1 = kidx / 64;
+ if (op1 == 2) {
+ op1 = 3;
+ }
+ crm = (kidx % 64) / 8;
+ op2 = kidx % 8;
+ sysreg = ENCODE_ID_REG(3, op1, 0, crm, op2);
+ return get_sysreg_idx(sysreg);
+}
+
static int idregs_idx_to_kvm_feature_idx(ARMIDRegisterIdx idx)
{
ARMSysRegs sysreg = id_register_sysreg[idx];
@@ -1189,6 +1204,40 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu)
return true;
}
+/*
+ * Copy writable ID regs from isar.idregs[] to cpreg_list
+ * in case their value differs from the original init cpreg value
+ */
+static void kvm_arm_writable_idregs_to_cpreg_list(ARMCPU *cpu)
+{
+ for (int i = 0; i < KVM_ARM_FEATURE_ID_RANGE_SIZE; i++) {
+ uint64_t writable_mask = cpu->writable_map[i];
+
+ if (writable_mask) {
+ int idx = kvm_feature_idx_to_idregs_idx(i);
+ ARM64SysReg *sysregdesc;
+ uint64_t previous, new;
+ uint64_t *cpreg;
+ uint32_t sysreg;
+
+ if (idx == -1) {
+ /* sysreg writable, but we don't know it */
+ continue;
+ }
+ sysregdesc = &arm64_id_regs[idx];
+ sysreg = id_register_sysreg[idx];
+ cpreg = kvm_arm_get_cpreg_ptr(cpu, idregs_sysreg_to_kvm_reg(sysreg));
+ previous = *cpreg;
+ new = cpu->isar.idregs[idx];
+ if (previous != new) {
+ *cpreg = new;
+ trace_kvm_arm_writable_idregs_to_cpreg_list(sysregdesc->name,
+ previous, new);
+ }
+ }
+ }
+}
+
void kvm_arm_reset_vcpu(ARMCPU *cpu)
{
int ret;
@@ -2140,7 +2189,25 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
- return kvm_arm_init_cpreg_list(cpu);
+ ret = kvm_arm_init_cpreg_list(cpu);
+ if (ret) {
+ return ret;
+ }
+ /* overwrite writable ID regs with their updated property values */
+ if (cpu->writable_map) {
+ kvm_arm_writable_idregs_to_cpreg_list(cpu);
+ ret = write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE);
+ if (!ret) {
+ return -1;
+ }
+ /*
+ * modified values may have changed the visibility of some regs,
+ * reinitialize the cpreg_list accordingly
+ */
+ ret = kvm_arm_init_cpreg_list(cpu);
+ }
+
+ return ret;
}
int kvm_arch_destroy_vcpu(CPUState *cs)
diff --git a/target/arm/trace-events b/target/arm/trace-events
index 8c7faf57c7..c25d2a1191 100644
--- a/target/arm/trace-events
+++ b/target/arm/trace-events
@@ -14,6 +14,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
# kvm.c
kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64
get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host value for %s is 0x%"PRIx64
+kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous, uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64
# cpu.c
arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64
--
2.53.0
next prev parent reply other threads:[~2026-05-19 13:30 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 13:27 [PATCH v5 00/18] kvm/arm: Introduce a customizable aarch64 KVM host model Eric Auger
2026-05-19 13:27 ` [PATCH v5 01/18] scripts: introduce scripts/update-aarch64-cpu-sysregs-header.py Eric Auger
2026-05-19 13:27 ` [PATCH v5 02/18] target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order Eric Auger
2026-06-01 14:07 ` Shameer Kolothum Thodi
2026-05-19 13:27 ` [PATCH v5 03/18] target/arm/cpu-sysregs.h.inc: Update with automatic generation Eric Auger
2026-06-01 14:09 ` Shameer Kolothum Thodi
2026-05-19 13:27 ` [PATCH v5 04/18] arm/cpu: Add infra to handle generated ID register definitions Eric Auger
2026-05-21 13:23 ` Sebastian Ott
2026-06-01 14:28 ` Shameer Kolothum Thodi
2026-06-12 7:38 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 05/18] scripts: Introduce scripts/aarch64_sysreg_helpers module Eric Auger
2026-05-19 13:27 ` [PATCH v5 06/18] scripts: Introduce scripts/update-aarch64-cpu-sysreg-properties.py Eric Auger
2026-05-27 14:35 ` Khushit Shah
2026-05-27 15:11 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 07/18] target/arm/cpu-idregs.h.inc: generate with script Eric Auger
2026-05-19 13:27 ` [PATCH v5 08/18] target/arm/cpu_idregs: generate tables for Arm64 ID registers and fields Eric Auger
2026-05-21 13:27 ` Sebastian Ott
2026-05-27 14:52 ` Khushit Shah
2026-05-27 15:14 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 09/18] target/arm/kvm: Introduce kvm_get_writable_id_regs Eric Auger
2026-05-21 13:43 ` Sebastian Ott
2026-06-01 15:26 ` Shameer Kolothum Thodi
2026-05-19 13:27 ` [PATCH v5 10/18] target/arm/cpu64: Retrieve writable ID reg map in aarch64_host_initfn() Eric Auger
2026-05-21 13:47 ` Sebastian Ott
2026-05-27 14:54 ` Khushit Shah
2026-05-27 15:17 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 11/18] arm/kvm: Initialize all writable ID registers from host Eric Auger
2026-05-21 14:22 ` Sebastian Ott
2026-05-27 15:02 ` Khushit Shah
2026-05-27 15:25 ` Eric Auger
2026-05-27 15:30 ` Eric Auger
2026-05-19 13:27 ` Eric Auger [this message]
2026-05-27 14:42 ` [PATCH v5 12/18] arm/kvm: write back modified ID regs to KVM Khushit Shah
2026-05-27 15:28 ` Khushit Shah
2026-05-27 15:33 ` Khushit Shah
2026-05-28 17:35 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 13/18] target/arm/kvm: Introduce kvm_arm_expose_idreg_properties Eric Auger
2026-05-26 14:42 ` Sebastian Ott
2026-05-27 15:08 ` Khushit Shah
2026-05-27 15:32 ` Eric Auger
2026-05-27 15:44 ` Khushit Shah
2026-05-27 16:19 ` Eric Auger
2026-05-28 5:07 ` Khushit Shah
2026-05-28 15:22 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 14/18] target/arm/kvm: Special case REVIDR_EL1 and AIDR_EL1 Eric Auger
2026-05-26 15:08 ` Sebastian Ott
2026-05-19 13:27 ` [PATCH v5 15/18] target/arm/kvm: Ignore some writable bits that shouldn't be Eric Auger
2026-05-27 14:46 ` Khushit Shah
2026-05-27 15:45 ` Eric Auger
2026-05-27 15:54 ` Khushit Shah
2026-05-27 16:01 ` Eric Auger
2026-05-27 16:16 ` Khushit Shah
2026-05-27 16:30 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 16/18] target/arm/cpu: Expose writable ID reg field properties on the kvm host vcpu model Eric Auger
2026-05-26 14:51 ` Sebastian Ott
2026-05-27 15:16 ` Khushit Shah
2026-05-27 15:51 ` Eric Auger
2026-05-27 15:56 ` Khushit Shah
2026-05-27 16:04 ` Eric Auger
2026-05-27 16:11 ` Khushit Shah
2026-05-27 17:20 ` Eric Auger
2026-05-28 5:29 ` Khushit Shah
2026-05-28 17:31 ` Eric Auger
2026-05-28 15:14 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 17/18] arm-qmp-cmds: introspection for ID register props Eric Auger
2026-05-27 6:29 ` Sebastian Ott
2026-05-27 15:17 ` Khushit Shah
2026-05-27 15:55 ` Eric Auger
2026-05-19 13:27 ` [PATCH v5 18/18] arm/cpu-features: document ID reg properties Eric Auger
2026-05-27 6:37 ` Sebastian Ott
2026-06-04 6:08 ` [PATCH v5 00/18] kvm/arm: Introduce a customizable aarch64 KVM host model Jinqian Yang
2026-06-04 6:32 ` Jinqian Yang
2026-06-04 8:31 ` Eric Auger
2026-06-04 12:00 ` Jinqian Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260519132905.145643-13-eric.auger@redhat.com \
--to=eric.auger@redhat.com \
--cc=abologna@redhat.com \
--cc=armbru@redhat.com \
--cc=berrange@redhat.com \
--cc=cohuck@redhat.com \
--cc=eric.auger.pro@gmail.com \
--cc=jdenemar@redhat.com \
--cc=khushit.shah@nutanix.com \
--cc=kvmarm@lists.linux.dev \
--cc=maz@kernel.org \
--cc=oliver.upton@linux.dev \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sebott@redhat.com \
--cc=shaju.abraham@nutanix.com \
--cc=skolothumtho@nvidia.com \
--cc=yangjinqian1@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.