* [PULL 01/37] hw/misc/aspeed_scu: Fix AST2600_RNG definitions
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 02/37] tests/functional/arm/test_aspeed_ast2600_sdk: Add USB EHCI test for AST2600 SDK Cédric Le Goater
` (36 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Cédric Le Goater, Jamin Lin
Commit e09cf36321f6 ("hw: aspeed_scu: Add AST2600 support") introduced
a typo on the definitions of the Random Number Generator registers.
Fix that.
The implementation of RNG_CTRL and RNG_DATA should be rechecked on HW
since the QEMU implementation always generates random data, regardless
of RNG_CTRL. A comment in aspeed_ast2600_scu_read() admits uncertainty
about the behavior :
/*
* On hardware, RNG_DATA works regardless of the state of the
* enable bit in RNG_CTRL
*
* TODO: Check this is true for ast2600
*/
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2350
Fixes: e09cf36321f6 ("hw: aspeed_scu: Add AST2600 support")
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_scu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index e4160356e443..9d9f43e6b563 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -128,8 +128,8 @@
#define AST2600_HW_STRAP2 TO_REG(0x510)
#define AST2600_HW_STRAP2_CLR TO_REG(0x514)
#define AST2600_HW_STRAP2_PROT TO_REG(0x518)
-#define AST2600_RNG_CTRL TO_REG(0x524)
-#define AST2600_RNG_DATA TO_REG(0x540)
+#define AST2600_RNG_CTRL TO_REG(0x520)
+#define AST2600_RNG_DATA TO_REG(0x524)
#define AST2600_CHIP_ID0 TO_REG(0x5B0)
#define AST2600_CHIP_ID1 TO_REG(0x5B4)
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 02/37] tests/functional/arm/test_aspeed_ast2600_sdk: Add USB EHCI test for AST2600 SDK
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
2026-05-26 8:18 ` [PULL 01/37] hw/misc/aspeed_scu: Fix AST2600_RNG definitions Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 03/37] tests/functional/aspeed: introduce FacebookAspeedTest Cédric Le Goater
` (35 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Jamin Lin, Philippe Mathieu-Daudé, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Add a functional test to verify USB EHCI support on the AST2600
SDK machine by attaching a USB keyboard device and checking its
enumeration via lsusb.
This introduces a helper routine that runs lsusb in the guest
and validates that the emulated "QEMU USB Keyboard" is detected.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260504025342.1452605-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/functional/arm/test_aspeed_ast2600_sdk.py | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functional/arm/test_aspeed_ast2600_sdk.py
index d787e90d1024..01548dd1354d 100755
--- a/tests/functional/arm/test_aspeed_ast2600_sdk.py
+++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py
@@ -40,6 +40,11 @@ def do_ast2600_i3c_test(self):
'i3ctransfer -d /dev/bus/i3c/5-1234567890ab -r 8 | grep 0x | xargs',
'0x12 0x34 0x56 0x78 0x90 0xab 0xcd 0xef')
+ def do_ast2600_usb_ehci_test(self):
+ exec_command_and_wait_for_pattern(self,
+ 'lsusb',
+ 'QEMU QEMU USB Keyboard')
+
def test_arm_ast2600_evb_sdk(self):
self.set_machine('ast2600-evb')
self.require_netdev('user')
@@ -54,6 +59,7 @@ def test_arm_ast2600_evb_sdk(self):
self.vm.add_args('-netdev', 'user,id=net1')
self.vm.add_args('-device',
'mock-i3c-target,bus=dw.i3c.5,pid=0xab9078563412')
+ self.vm.add_args('-device', 'usb-kbd,bus=usb-bus.1')
self.do_test_arm_aspeed_sdk_start(
self.scratch_file("ast2600-default-image", "image-bmc"))
@@ -81,6 +87,7 @@ def test_arm_ast2600_evb_sdk(self):
'/sbin/hwclock -f /dev/rtc1', year)
self.do_ast2600_pcie_test()
self.do_ast2600_i3c_test()
+ self.do_ast2600_usb_ehci_test()
if __name__ == '__main__':
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 03/37] tests/functional/aspeed: introduce FacebookAspeedTest
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
2026-05-26 8:18 ` [PULL 01/37] hw/misc/aspeed_scu: Fix AST2600_RNG definitions Cédric Le Goater
2026-05-26 8:18 ` [PULL 02/37] tests/functional/arm/test_aspeed_ast2600_sdk: Add USB EHCI test for AST2600 SDK Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 04/37] hw/arm/aspeed: add anacapa-bmc machine Cédric Le Goater
` (34 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: William de Abreu Pinho, Cédric Le Goater
From: William de Abreu Pinho <williamdapinho@gmail.com>
Facebook OpenBMC Images include an early script [1] that lowers the
console log level to warning. This suppresses the "Hostname set to"
message from the serial console. Introduce FacebookAspeedTest (a
subclass of AspeedTest), that waits for login prompt instead. Update
bletchley-bmc and catalina-bmc to use the new class.
This is also used by the anacapa-bmc machine introduced in the following
patch.
[1]: https://github.com/openbmc/openbmc/blob/6a56a45931fb7015a3fc18553415909105b484d6/meta-facebook/recipes-phosphor/initrdscripts/phosphor-static-norootfs-init/999-reduce-printk
Signed-off-by: William de Abreu Pinho <williamdapinho@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260519-add-anacapa-machine-v3-1-56c23993a20a@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/functional/arm/test_aspeed_bletchley.py | 6 +++---
tests/functional/arm/test_aspeed_catalina.py | 6 +++---
tests/functional/aspeed.py | 8 ++++++++
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/tests/functional/arm/test_aspeed_bletchley.py b/tests/functional/arm/test_aspeed_bletchley.py
index 5a60b24b3d2c..3000d0c302b1 100755
--- a/tests/functional/arm/test_aspeed_bletchley.py
+++ b/tests/functional/arm/test_aspeed_bletchley.py
@@ -5,10 +5,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
from qemu_test import Asset
-from aspeed import AspeedTest
+from aspeed import FacebookAspeedTest
-class BletchleyMachine(AspeedTest):
+class BletchleyMachine(FacebookAspeedTest):
ASSET_BLETCHLEY_FLASH = Asset(
'https://github.com/legoater/qemu-aspeed-boot/raw/master/images/bletchley-bmc/openbmc-20250128071329/obmc-phosphor-image-bletchley-20250128071329.static.mtd.xz',
@@ -22,4 +22,4 @@ def test_arm_ast2600_bletchley_openbmc(self):
soc='AST2600 rev A3')
if __name__ == '__main__':
- AspeedTest.main()
+ FacebookAspeedTest.main()
diff --git a/tests/functional/arm/test_aspeed_catalina.py b/tests/functional/arm/test_aspeed_catalina.py
index dc2f24e7b43c..2694e4b005b7 100755
--- a/tests/functional/arm/test_aspeed_catalina.py
+++ b/tests/functional/arm/test_aspeed_catalina.py
@@ -5,10 +5,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
from qemu_test import Asset
-from aspeed import AspeedTest
+from aspeed import FacebookAspeedTest
-class CatalinaMachine(AspeedTest):
+class CatalinaMachine(FacebookAspeedTest):
ASSET_CATALINA_FLASH = Asset(
'https://github.com/legoater/qemu-aspeed-boot/raw/a866feb5ef81245b4827a214584bf6bcc72939f6/images/catalina-bmc/obmc-phosphor-image-catalina-20250619123021.static.mtd.xz',
@@ -22,4 +22,4 @@ def test_arm_ast2600_catalina_openbmc(self):
soc='AST2600 rev A3')
if __name__ == '__main__':
- AspeedTest.main()
+ FacebookAspeedTest.main()
diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
index 47e84e035bd0..88b659093467 100644
--- a/tests/functional/aspeed.py
+++ b/tests/functional/aspeed.py
@@ -28,6 +28,9 @@ def do_test_arm_aspeed_openbmc(self, machine, image, uboot='2019.04',
self.wait_for_console_pattern(f'Booting Linux on physical CPU {cpu_id}')
self.wait_for_console_pattern(f'ASPEED {soc}')
self.wait_for_console_pattern('/init as init process')
+ self.wait_for_boot_complete(hostname)
+
+ def wait_for_boot_complete(self, hostname):
self.wait_for_console_pattern(f'systemd[1]: Hostname set to <{hostname}>.')
def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
@@ -69,3 +72,8 @@ def generate_otpmem_image(self):
f.write(pattern)
return path
+
+class FacebookAspeedTest(AspeedTest):
+
+ def wait_for_boot_complete(self, hostname):
+ self.wait_for_console_pattern(f'{hostname} login:')
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 04/37] hw/arm/aspeed: add anacapa-bmc machine
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (2 preceding siblings ...)
2026-05-26 8:18 ` [PULL 03/37] tests/functional/aspeed: introduce FacebookAspeedTest Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 05/37] hw/arm/aspeed: anacapa: add FRU EEPROM data Cédric Le Goater
` (33 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: William de Abreu Pinho, Cédric Le Goater
From: William de Abreu Pinho <williamdapinho@gmail.com>
Add the Facebook Anacapa BMC machine. The I2C topology is based on the
Linux kernel device tree [1]. Hardware strap register values are taken
from real hardware.
A functional test is included using the OpenBMC image built from [2],
similar to the tests for bletchley-bmc and catalina-bmc.
[1]: https://github.com/torvalds/linux/blob/76b4ec8efdc3887cdbf730da2e55881fc1a18770/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
[2]: https://github.com/openbmc/openbmc/commit/8e22df918eaaa5d83143471d24ef0eeb1c1e3c7c
Signed-off-by: William de Abreu Pinho <williamdapinho@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260519-add-anacapa-machine-v3-2-56c23993a20a@gmail.com
[ clg: docs/system/arm/aspeed.rst : fixed 'Aspeed family boards' title change ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
docs/system/arm/aspeed.rst | 5 +-
hw/arm/aspeed_ast2600_anacapa.c | 153 ++++++++++++++++++++
hw/arm/meson.build | 1 +
tests/functional/arm/meson.build | 2 +
tests/functional/arm/test_aspeed_anacapa.py | 25 ++++
5 files changed, 184 insertions(+), 2 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_anacapa.c
create mode 100644 tests/functional/arm/test_aspeed_anacapa.py
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index df2f539b0257..a2eccf54892d 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -1,5 +1,5 @@
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
-==============================================================================================================================================================================================================================================================================================================================
+Aspeed family boards (``anacapa-bmc``, ``ast2500-evb``, ``ast2600-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
+===============================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
Aspeed evaluation boards. They are based on different releases of the
@@ -33,6 +33,7 @@ AST2600 SoC based machines :
- ``fuji-bmc`` Facebook Fuji BMC
- ``bletchley-bmc`` Facebook Bletchley BMC
- ``fby35-bmc`` Facebook fby35 BMC
+- ``anacapa-bmc`` Facebook Anacapa BMC
- ``gb200nvl-bmc`` Nvidia GB200nvl BMC
Supported devices
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
new file mode 100644
index 000000000000..c24f00d44cde
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -0,0 +1,153 @@
+/*
+ * Facebook Anacapa
+ *
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/machines-qom.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/i2c_mux_pca954x.h"
+#include "hw/gpio/pca9552.h"
+#include "hw/nvram/eeprom_at24c.h"
+
+/* Anacapa hardware value */
+#define ANACAPA_BMC_HW_STRAP1 0x00002002
+#define ANACAPA_BMC_HW_STRAP2 0x00000000
+#define ANACAPA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
+
+static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ /* Reference: aspeed-bmc-facebook-anacapa.dts */
+
+ AspeedSoCState *soc = bmc->soc;
+ I2CBus *i2c[16] = {};
+ I2CSlave *i2c_mux;
+
+ for (int i = 0; i < ARRAY_SIZE(i2c); i++) {
+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+ }
+
+ /* &i2c0 */
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[0], 0x50, 256 * KiB);
+ /* i2c-mux@70 */
+ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x70);
+
+ /* &i2c1 */
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[1], 0x50, 256 * KiB);
+ /* i2c-mux@70 (PCA9546) — 4 channels, empty */
+ i2c_slave_create_simple(i2c[1], TYPE_PCA9546, 0x70);
+
+ /* &i2c4 */
+ /* i2c-mux@70 (PCA9548) */
+ i2c_slave_create_simple(i2c[4], TYPE_PCA9548, 0x70);
+
+ /* &i2c6 */
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[6], 0x50, 32 * KiB);
+
+ /* &i2c8 */
+ /* i2c-mux@72 (PCA9546) */
+ i2c_mux = i2c_slave_create_simple(i2c[8], TYPE_PCA9546, 0x72);
+
+ /* i2c8mux ch0 */
+ /* adc128d818@1f — no model */
+ /* pca9555@22 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0),
+ TYPE_PCA9552, 0x22);
+ /* pca9555@24 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0),
+ TYPE_PCA9552, 0x24);
+ /* eeprom@50 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 16 * KiB);
+
+ /* i2c8mux ch1 */
+ /* pca9555@22 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
+ TYPE_PCA9552, 0x22);
+ /* pca9555@24 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
+ TYPE_PCA9552, 0x24);
+ /* eeprom@50 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 16 * KiB);
+
+ /* &i2c9 */
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[9], 0x50, 16 * KiB);
+ /* eeprom@56 */
+ at24c_eeprom_init(i2c[9], 0x56, 8 * KiB);
+
+ /* &i2c10 */
+ /* i2c-mux@71 (PCA9548) */
+ i2c_mux = i2c_slave_create_simple(i2c[10], TYPE_PCA9548, 0x71);
+
+ /* i2c10mux ch5 */
+ /* pca9555@22*/
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5),
+ TYPE_PCA9552, 0x22);
+ /* eeprom@52 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x52, 32 * KiB);
+
+ /* &i2c11 */
+ /* i2c-mux@71 (PCA9548) */
+ i2c_mux = i2c_slave_create_simple(i2c[11], TYPE_PCA9548, 0x71);
+
+ /* i2c11mux ch0-ch4 — empty */
+
+ /* i2c11mux ch5 */
+ /* pca9555@22 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5),
+ TYPE_PCA9552, 0x22);
+ /* eeprom@52 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x52, 32 * KiB);
+
+ /* &i2c13 */
+ /* i2c-mux@70 (PCA9548) */
+ i2c_mux = i2c_slave_create_simple(i2c[13], TYPE_PCA9548, 0x70);
+
+ /* i2c13mux ch3 */
+ /* adc128d818@1f - no model */
+
+ /* i2c13mux ch4 */
+ /* eeprom@51 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 4), 0x51, 32 * KiB);
+
+ /* i2c13mux ch7 */
+ /* nfc@28 — no model */
+}
+
+static void aspeed_machine_anacapa_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook Anacapa BMC (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = ANACAPA_BMC_HW_STRAP1;
+ amc->hw_strap2 = ANACAPA_BMC_HW_STRAP2;
+ amc->fmc_model = "mx66l1g45g";
+ amc->spi_model = NULL;
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON;
+ amc->i2c_init = anacapa_bmc_i2c_init;
+ mc->default_ram_size = ANACAPA_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast2600_anacapa_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("anacapa-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_anacapa_class_init,
+ .interfaces = arm_machine_interfaces,
+ }
+};
+
+DEFINE_TYPES(aspeed_ast2600_anacapa_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 80068f70bb9c..4fe7efd189e2 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -54,6 +54,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2500_witherspoon.c',
'aspeed_ast2500_yosemitev2.c',
'aspeed_ast2600.c',
+ 'aspeed_ast2600_anacapa.c',
'aspeed_ast2600_bletchley.c',
'aspeed_ast2600_catalina.c',
'aspeed_ast2600_evb.c',
diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.build
index 2f538f29a2de..959179a56f6d 100644
--- a/tests/functional/arm/meson.build
+++ b/tests/functional/arm/meson.build
@@ -12,6 +12,7 @@ test_arm_timeouts = {
'aspeed_ast2600_sdk' : 720,
'aspeed_ast2600_sdk_515' : 720,
'aspeed_ast2600_sdk_otp' : 720,
+ 'aspeed_anacapa' : 480,
'aspeed_bletchley' : 480,
'aspeed_catalina' : 480,
'aspeed_gb200nvl_bmc' : 480,
@@ -45,6 +46,7 @@ tests_arm_system_thorough = [
'aspeed_ast2600_sdk',
'aspeed_ast2600_sdk_515',
'aspeed_ast2600_sdk_otp',
+ 'aspeed_anacapa',
'aspeed_bletchley',
'aspeed_catalina',
'aspeed_gb200nvl_bmc',
diff --git a/tests/functional/arm/test_aspeed_anacapa.py b/tests/functional/arm/test_aspeed_anacapa.py
new file mode 100644
index 000000000000..27f8bd8b56a8
--- /dev/null
+++ b/tests/functional/arm/test_aspeed_anacapa.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset
+from aspeed import FacebookAspeedTest
+
+
+class AnacapaMachine(FacebookAspeedTest):
+
+ ASSET_ANACAPA_FLASH = Asset(
+ 'https://github.com/legoater/qemu-aspeed-boot/raw/3fa3212827b04be4034d43b5adeef57c27d6ab18/images/anacapa-bmc/openbmc-20260512025228/obmc-phosphor-image-anacapa-20260512025228.static.mtd.xz',
+ '2232e241abcfb6d4f6b82cb6c378ce5ce05e364aac6d118785c2b6cc33fe43f3')
+
+ def test_arm_ast2600_anacapa_openbmc(self):
+ image_path = self.uncompress(self.ASSET_ANACAPA_FLASH)
+
+ self.do_test_arm_aspeed_openbmc('anacapa-bmc', image=image_path,
+ uboot='2019.04', cpu_id='0xf00',
+ soc='AST2600 rev A3')
+
+if __name__ == '__main__':
+ FacebookAspeedTest.main()
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 05/37] hw/arm/aspeed: anacapa: add FRU EEPROM data
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (3 preceding siblings ...)
2026-05-26 8:18 ` [PULL 04/37] hw/arm/aspeed: add anacapa-bmc machine Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 06/37] hw/arm/aspeed: Convert SRAM MemoryRegion to array type Cédric Le Goater
` (32 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: William de Abreu Pinho, Cédric Le Goater
From: William de Abreu Pinho <williamdapinho@gmail.com>
Use frugen to generate FRU data for the following components: HPM MB,
R-PDB, L-PDB, SCM, BSM, R Bridge Board, L Bridge Board, and HPM board
ID.
Signed-off-by: William de Abreu Pinho <williamdapinho@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260519-add-anacapa-machine-v3-3-56c23993a20a@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast2600_anacapa.c | 225 ++++++++++++++++++++++++++++++--
1 file changed, 217 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
index c24f00d44cde..a1c8111a9344 100644
--- a/hw/arm/aspeed_ast2600_anacapa.c
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -20,6 +20,207 @@
#define ANACAPA_BMC_HW_STRAP2 0x00000000
#define ANACAPA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
+/*
+ * "Anacapa HPM (MB)" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Inventec", "pname": "Anacapa QEMU MB EVT2",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Inventec", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t hpm_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0xf6, 0x01, 0x07, 0x19, 0xb4,
+ 0xa4, 0xf2, 0xc8, 0x49, 0x6e, 0x76, 0x65, 0x6e, 0x74, 0x65, 0x63, 0xd4,
+ 0x41, 0x6e, 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x51, 0x45, 0x4d, 0x55,
+ 0x20, 0x4d, 0x42, 0x20, 0x45, 0x56, 0x54, 0x32, 0x47, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xc0,
+ 0xc1, 0x00, 0x00, 0xb8, 0x01, 0x06, 0x19, 0xc8, 0x49, 0x6e, 0x76, 0x65,
+ 0x6e, 0x74, 0x65, 0x63, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e, 0x61, 0x63,
+ 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x82, 0x2d,
+ 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x71, 0xd9,
+ 0xd6, 0xc0, 0xc1, 0x0e
+};
+static const size_t hpm_eeprom_len = sizeof(hpm_eeprom);
+
+/*
+ * "Anacapa R-PDB" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Inventec", "pname": "Anacapa QEMU RPDB",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Inventec", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t rpdb_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0xf6, 0x01, 0x07, 0x19, 0x41,
+ 0x2d, 0xf2, 0xc8, 0x49, 0x6e, 0x76, 0x65, 0x6e, 0x74, 0x65, 0x63, 0xd1,
+ 0x41, 0x6e, 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x51, 0x45, 0x4d, 0x55,
+ 0x20, 0x52, 0x50, 0x44, 0x42, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xc0, 0xc1, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4d, 0x01, 0x06, 0x19, 0xc8, 0x49, 0x6e, 0x76, 0x65,
+ 0x6e, 0x74, 0x65, 0x63, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e, 0x61, 0x63,
+ 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x82, 0x2d,
+ 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x71, 0xd9,
+ 0xd6, 0xc0, 0xc1, 0x0e
+};
+static const size_t rpdb_eeprom_len = sizeof(rpdb_eeprom);
+
+/*
+ * "Anacapa L-PDB" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Inventec", "pname": "Anacapa QEMU LPDB",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Inventec", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t lpdb_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0xf6, 0x01, 0x07, 0x19, 0x41,
+ 0x2d, 0xf2, 0xc8, 0x49, 0x6e, 0x76, 0x65, 0x6e, 0x74, 0x65, 0x63, 0xd1,
+ 0x41, 0x6e, 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x51, 0x45, 0x4d, 0x55,
+ 0x20, 0x4c, 0x50, 0x44, 0x42, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xc0, 0xc1, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x53, 0x01, 0x06, 0x19, 0xc8, 0x49, 0x6e, 0x76, 0x65,
+ 0x6e, 0x74, 0x65, 0x63, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e, 0x61, 0x63,
+ 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x82, 0x2d,
+ 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x71, 0xd9,
+ 0xd6, 0xc0, 0xc1, 0x0e
+};
+static const size_t lpdb_eeprom_len = sizeof(lpdb_eeprom);
+
+/*
+ * "Anacapa SCM" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Quanta", "pname": "Anacapa SCM",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Quanta", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t scm_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x07, 0x00, 0x00, 0xf7, 0x01, 0x06, 0x19, 0x41,
+ 0x2d, 0xf2, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x41, 0x6e,
+ 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x53, 0x43, 0x4d, 0x47, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x06, 0x19, 0xc6,
+ 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e,
+ 0x61, 0x63, 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a,
+ 0x82, 0x2d, 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83,
+ 0x71, 0xd9, 0xd6, 0xc0, 0xc1, 0x00, 0x00, 0xe2
+};
+static const size_t scm_eeprom_len = sizeof(scm_eeprom);
+
+/*
+ * "Anacapa BMC Storage Module" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Quanta", "pname": "Anacapa BMC Storage Module",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Quanta", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t bsm_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x00, 0x00,
+ 0x00, 0x00, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xda, 0x41, 0x6e,
+ 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x42, 0x4d, 0x43, 0x20, 0x53, 0x74,
+ 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f, 0x64, 0x75, 0x6c, 0x65,
+ 0xce, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+ 0x30, 0x30, 0x30, 0xcb, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+ 0x30, 0x30, 0x30, 0xc0, 0xc1, 0x00, 0x00, 0x10, 0x01, 0x08, 0x00, 0xc6,
+ 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e,
+ 0x61, 0x63, 0x61, 0x70, 0x61, 0xcb, 0x31, 0x30, 0x30, 0x30, 0x30, 0x30,
+ 0x30, 0x30, 0x30, 0x30, 0x31, 0xc2, 0x4d, 0x50, 0xce, 0x31, 0x30, 0x30,
+ 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0xc4,
+ 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+};
+static const size_t bsm_eeprom_len = sizeof(bsm_eeprom);
+
+/*
+ * "Anacapa R Bridge Board" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Inventec", "pname": "Anacapa QEMU RBB EVT2",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Inventec", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t rbb_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0xf6, 0x01, 0x07, 0x19, 0xb4,
+ 0xa4, 0xf2, 0xc8, 0x49, 0x6e, 0x76, 0x65, 0x6e, 0x74, 0x65, 0x63, 0xd5,
+ 0x41, 0x6e, 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x51, 0x45, 0x4d, 0x55,
+ 0x20, 0x52, 0x42, 0x42, 0x20, 0x45, 0x56, 0x54, 0x32, 0x47, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0xc0, 0xc1, 0x00, 0x70, 0x01, 0x06, 0x19, 0xc8, 0x49, 0x6e, 0x76, 0x65,
+ 0x6e, 0x74, 0x65, 0x63, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e, 0x61, 0x63,
+ 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x82, 0x2d,
+ 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x71, 0xd9,
+ 0xd6, 0xc0, 0xc1, 0x0e
+};
+static const size_t rbb_eeprom_len = sizeof(rbb_eeprom);
+
+/*
+ * "Anacapa L Bridge Board" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Inventec", "pname": "Anacapa QEMU LBB EVT2",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Inventec", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t lbb_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0xf6, 0x01, 0x07, 0x19, 0xb4,
+ 0xa4, 0xf2, 0xc8, 0x49, 0x6e, 0x76, 0x65, 0x6e, 0x74, 0x65, 0x63, 0xd5,
+ 0x41, 0x6e, 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x51, 0x45, 0x4d, 0x55,
+ 0x20, 0x4c, 0x42, 0x42, 0x20, 0x45, 0x56, 0x54, 0x32, 0x47, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+ 0xc0, 0xc1, 0x00, 0x76, 0x01, 0x06, 0x19, 0xc8, 0x49, 0x6e, 0x76, 0x65,
+ 0x6e, 0x74, 0x65, 0x63, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e, 0x61, 0x63,
+ 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x82, 0x2d,
+ 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x71, 0xd9,
+ 0xd6, 0xc0, 0xc1, 0x0e
+};
+static const size_t lbb_eeprom_len = sizeof(lbb_eeprom);
+
+/*
+ * "Anacapa HPM BRD ID" FRU data. Generated with frugen.
+ *
+ * {
+ * "board": { "mfg": "Inventec", "pname": "Anacapa HPM BRD ID",
+ * "pn": "00000000000", "serial": "00000000000000" },
+ * "product": { "mfg": "Inventec", "pname": "CI-Anacapa",
+ * "pn": "10000000001", "ver": "MP",
+ * "serial": "10000000000000", "atag": "QEMU" }
+ * }
+ */
+static const uint8_t hpm_brd_id_eeprom[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0xf6, 0x01, 0x07, 0x19, 0x41,
+ 0x2d, 0xf2, 0xc8, 0x49, 0x6e, 0x76, 0x65, 0x6e, 0x74, 0x65, 0x63, 0xd2,
+ 0x41, 0x6e, 0x61, 0x63, 0x61, 0x70, 0x61, 0x20, 0x48, 0x50, 0x4d, 0x20,
+ 0x42, 0x52, 0x44, 0x20, 0x49, 0x44, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xc0, 0xc1, 0x00,
+ 0x00, 0x00, 0x00, 0x42, 0x01, 0x06, 0x19, 0xc8, 0x49, 0x6e, 0x76, 0x65,
+ 0x6e, 0x74, 0x65, 0x63, 0xca, 0x43, 0x49, 0x2d, 0x41, 0x6e, 0x61, 0x63,
+ 0x61, 0x70, 0x61, 0x46, 0x10, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x82, 0x2d,
+ 0x0c, 0x47, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x71, 0xd9,
+ 0xd6, 0xc0, 0xc1, 0x0e
+};
+static const size_t hpm_brd_id_eeprom_len = sizeof(hpm_brd_id_eeprom);
+
static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
{
/* Reference: aspeed-bmc-facebook-anacapa.dts */
@@ -50,7 +251,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
/* &i2c6 */
/* eeprom@50 */
- at24c_eeprom_init(i2c[6], 0x50, 32 * KiB);
+ at24c_eeprom_init_rom(i2c[6], 0x50, 32 * KiB,
+ hpm_eeprom, hpm_eeprom_len);
/* &i2c8 */
/* i2c-mux@72 (PCA9546) */
@@ -65,7 +267,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0),
TYPE_PCA9552, 0x24);
/* eeprom@50 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 16 * KiB);
+ at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 16 * KiB,
+ rpdb_eeprom, rpdb_eeprom_len);
/* i2c8mux ch1 */
/* pca9555@22 */
@@ -75,13 +278,16 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
TYPE_PCA9552, 0x24);
/* eeprom@50 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 16 * KiB);
+ at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 16 * KiB,
+ lpdb_eeprom, lpdb_eeprom_len);
/* &i2c9 */
/* eeprom@50 */
- at24c_eeprom_init(i2c[9], 0x50, 16 * KiB);
+ at24c_eeprom_init_rom(i2c[9], 0x50, 16 * KiB,
+ scm_eeprom, scm_eeprom_len);
/* eeprom@56 */
- at24c_eeprom_init(i2c[9], 0x56, 8 * KiB);
+ at24c_eeprom_init_rom(i2c[9], 0x56, 8 * KiB,
+ bsm_eeprom, bsm_eeprom_len);
/* &i2c10 */
/* i2c-mux@71 (PCA9548) */
@@ -92,7 +298,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5),
TYPE_PCA9552, 0x22);
/* eeprom@52 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x52, 32 * KiB);
+ at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 5), 0x52, 32 * KiB,
+ rbb_eeprom, rbb_eeprom_len);
/* &i2c11 */
/* i2c-mux@71 (PCA9548) */
@@ -105,7 +312,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5),
TYPE_PCA9552, 0x22);
/* eeprom@52 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x52, 32 * KiB);
+ at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 5), 0x52, 32 * KiB,
+ lbb_eeprom, lbb_eeprom_len);
/* &i2c13 */
/* i2c-mux@70 (PCA9548) */
@@ -116,7 +324,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
/* i2c13mux ch4 */
/* eeprom@51 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 4), 0x51, 32 * KiB);
+ at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 4), 0x51, 32 * KiB,
+ hpm_brd_id_eeprom, hpm_brd_id_eeprom_len);
/* i2c13mux ch7 */
/* nfc@28 — no model */
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 06/37] hw/arm/aspeed: Convert SRAM MemoryRegion to array type
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (4 preceding siblings ...)
2026-05-26 8:18 ` [PULL 05/37] hw/arm/aspeed: anacapa: add FRU EEPROM data Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 07/37] hw/arm/aspeed: Convert SRAM size definition " Cédric Le Goater
` (31 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Several kinds of RAM are supported across Aspeed SoCs, including
SRAM, SDRAM, HyperRAM, secure SRAM, and generic SRAM. In addition,
different SoCs may expose multiple SRAM regions at different MMIO
addresses.
The current implementation models SRAM with a single MemoryRegion
instance, which makes future expansion cumbersome when additional
SRAM types or regions are introduced.
Prepare for future SoC designs by converting the SRAM MemoryRegion
from a single object into an array-based structure. This change
introduces ASPEED_SRAM_NUM and converts existing SRAM users to
reference sram[0].
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 3 ++-
hw/arm/aspeed_ast10x0.c | 5 +++--
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 6 +++---
hw/arm/aspeed_ast27x0.c | 4 ++--
5 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index d7b3647ca16c..e6942b2936ae 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -60,6 +60,7 @@
#define ASPEED_PCIE_NUM 3
#define ASPEED_INTC_NUM 2
#define ASPEED_IOEXP_NUM 2
+#define ASPEED_SRAM_NUM 1
struct AspeedSoCState {
DeviceState parent;
@@ -67,7 +68,7 @@ struct AspeedSoCState {
MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
- MemoryRegion sram;
+ MemoryRegion sram[ASPEED_SRAM_NUM];
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
MemoryRegion vbootrom;
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 41a4e82c1f87..3e478f752058 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -240,14 +240,15 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
/* Internal SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d",
CPU(a->armv7m.cpu)->cpu_index);
- memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_size,
+ &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
- &s->sram);
+ &s->sram[0]);
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
sc->secsram_size, &err);
if (err != NULL) {
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index b1b826b7e0b1..d79aa832f3fa 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -281,12 +281,12 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index efb1d8c0637c..a69103de89ea 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -437,12 +437,12 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
/* DPMCU */
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 87dcb82e1b01..0fb5e4b24c9d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -778,12 +778,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_size,
errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
/* VBOOTROM */
if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 07/37] hw/arm/aspeed: Convert SRAM size definition to array type
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (5 preceding siblings ...)
2026-05-26 8:18 ` [PULL 06/37] hw/arm/aspeed: Convert SRAM MemoryRegion to array type Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 08/37] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support Cédric Le Goater
` (30 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Prepare the Aspeed SoC model for future platforms that may contain
multiple SRAM regions with different sizes and MMIO mappings.
The current implementation stores SRAM size information in a single
sram_size field, which limits extensibility when additional SRAM
instances are introduced.
Convert sram_size into an array-based definition and update all
existing users to reference sram_size[0]. This aligns with the
previous SRAM MemoryRegion array conversion and provides a scalable
foundation for supporting multiple SRAM regions in future SoCs.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast10x0.c | 8 ++++----
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_ast27x0.c | 8 ++++----
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index e6942b2936ae..3a7db959a9ae 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -172,7 +172,7 @@ struct AspeedSoCClass {
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
uint32_t silicon_rev;
- uint64_t sram_size;
+ uint64_t sram_size[ASPEED_SRAM_NUM];
uint64_t secsram_size;
int pcie_num;
int spis_num;
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 3e478f752058..9e597a75ec53 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -240,8 +240,8 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
/* Internal SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d",
CPU(a->armv7m.cpu)->cpu_index);
- memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_size,
- &err);
+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size[0], &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
@@ -493,7 +493,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1030_A1_SILICON_REV;
- sc->sram_size = 0xc0000;
+ sc->sram_size[0] = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
@@ -521,7 +521,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1060_A2_SILICON_REV;
- sc->sram_size = 0xc0000;
+ sc->sram_size[0] = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
sc->spis_num = 2;
sc->wdts_num = 4;
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index d79aa832f3fa..c4e5388999e6 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -282,7 +282,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
- sc->sram_size, errp)) {
+ sc->sram_size[0], errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -533,7 +533,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2400_A1_SILICON_REV;
- sc->sram_size = 0x8000;
+ sc->sram_size[0] = 0x8000;
sc->spis_num = 1;
sc->ehcis_num = 1;
sc->wdts_num = 2;
@@ -560,7 +560,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2500_A1_SILICON_REV;
- sc->sram_size = 0x9000;
+ sc->sram_size[0] = 0x9000;
sc->spis_num = 2;
sc->ehcis_num = 2;
sc->wdts_num = 3;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a69103de89ea..2f8f49a37689 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -438,7 +438,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
- sc->sram_size, errp)) {
+ sc->sram_size[0], errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -764,7 +764,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2600_A3_SILICON_REV;
- sc->sram_size = 0x16400;
+ sc->sram_size[0] = 0x16400;
sc->spis_num = 2;
sc->ehcis_num = 2;
sc->wdts_num = 4;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 0fb5e4b24c9d..30883ea7ce40 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -778,8 +778,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name,
+ sc->sram_size[0], errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -1151,7 +1151,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
- sc->sram_size = 0x20000;
+ sc->sram_size[0] = 0x20000;
sc->pcie_num = 3;
sc->spis_num = 3;
sc->sgpio_num = 2;
@@ -1181,7 +1181,7 @@ static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A2_SILICON_REV;
- sc->sram_size = 0x20000;
+ sc->sram_size[0] = 0x20000;
sc->pcie_num = 3;
sc->spis_num = 3;
sc->sgpio_num = 2;
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 08/37] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (6 preceding siblings ...)
2026-05-26 8:18 ` [PULL 07/37] hw/arm/aspeed: Convert SRAM size definition " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 09/37] hw/arm/aspeed: Consolidate secure SRAM into SRAM array Cédric Le Goater
` (29 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Some Aspeed SoCs contain multiple SRAM regions with different
MMIO mappings, such as internal SRAM and secure SRAM.
Prepare for future multi-SRAM support by renaming the SRAM
memmap entry from ASPEED_DEV_SRAM to ASPEED_DEV_SRAM0.
This makes the numbering explicit and aligns with the
array-based SRAM representation introduced previously.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast10x0.c | 4 ++--
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_ast27x0-ssp.c | 4 ++--
hw/arm/aspeed_ast27x0-tsp.c | 4 ++--
hw/arm/aspeed_ast27x0.c | 4 ++--
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3a7db959a9ae..dda602e9f20c 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -228,7 +228,7 @@ enum {
ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
- ASPEED_DEV_SRAM,
+ ASPEED_DEV_SRAM0,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 9e597a75ec53..b55f788342a6 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -20,7 +20,7 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast1030_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM0] = 0x00000000,
[ASPEED_DEV_SECSRAM] = 0x79000000,
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
@@ -247,7 +247,7 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
return false;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
+ sc->memmap[ASPEED_DEV_SRAM0],
&s->sram[0]);
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
sc->secsram_size, &err);
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index c4e5388999e6..79a653f65f09 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -38,7 +38,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SRAM0] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
@@ -75,7 +75,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SRAM0] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
@@ -286,7 +286,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 2f8f49a37689..d1f18e471aa0 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -23,7 +23,7 @@
static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SRAM0] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x18000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
[ASPEED_DEV_IOMEM] = 0x1E600000,
@@ -442,7 +442,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* DPMCU */
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 8b84300e0f60..b3c4eb1915ed 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -20,7 +20,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x70000000,
+ [ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
@@ -182,7 +182,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index e7c7b744919b..6098d1aae32d 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -20,7 +20,7 @@
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x70000000,
+ [ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
@@ -182,7 +182,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 30883ea7ce40..d7ce14e8c563 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -30,7 +30,7 @@
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x00020000,
- [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SRAM0] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x11000000,
[ASPEED_DEV_IOMEM0] = 0x12000000,
[ASPEED_DEV_EHCI1] = 0x12061000,
@@ -783,7 +783,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* VBOOTROM */
if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 09/37] hw/arm/aspeed: Consolidate secure SRAM into SRAM array
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (7 preceding siblings ...)
2026-05-26 8:18 ` [PULL 08/37] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 10/37] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID Cédric Le Goater
` (28 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Some Aspeed SoCs contain multiple SRAM regions with different
sizes and MMIO mappings, such as internal SRAM and secure SRAM.
The current implementation models secure SRAM separately from the
generic SRAM representation, which complicates future multi-SRAM
support and expansion.
Increase ASPEED_SRAM_NUM to 2 and migrate secure SRAM to use the
common SRAM array representation. Rename the secure SRAM memmap
entry to ASPEED_DEV_SRAM1 and update AST10x0 to initialize both
SRAM regions through sram[] and sram_size[].
This unifies SRAM-like regions under a common representation and
prepares for future SoCs with additional SRAM regions.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 6 ++----
hw/arm/aspeed_ast10x0.c | 16 +++++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index dda602e9f20c..3aac144cd408 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -60,7 +60,7 @@
#define ASPEED_PCIE_NUM 3
#define ASPEED_INTC_NUM 2
#define ASPEED_IOEXP_NUM 2
-#define ASPEED_SRAM_NUM 1
+#define ASPEED_SRAM_NUM 2
struct AspeedSoCState {
DeviceState parent;
@@ -89,7 +89,6 @@ struct AspeedSoCState {
AspeedSBCState sbc;
AspeedSLIState sli;
AspeedSLIState sliio;
- MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
AspeedPWMState pwm;
@@ -173,7 +172,6 @@ struct AspeedSoCClass {
const char * const *valid_cpu_types;
uint32_t silicon_rev;
uint64_t sram_size[ASPEED_SRAM_NUM];
- uint64_t secsram_size;
int pcie_num;
int spis_num;
int sgpio_num;
@@ -225,10 +223,10 @@ enum {
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_SBC,
- ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM0,
+ ASPEED_DEV_SRAM1,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index b55f788342a6..93c81195b56a 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -21,7 +21,7 @@
static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SRAM0] = 0x00000000,
- [ASPEED_DEV_SECSRAM] = 0x79000000,
+ [ASPEED_DEV_SRAM1] = 0x79000000, /* SEC SRAM */
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
[ASPEED_DEV_FMC] = 0x7E620000,
@@ -249,14 +249,16 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM0],
&s->sram[0]);
- memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
- sc->secsram_size, &err);
+
+ /* Internal SEC SRAM */
+ memory_region_init_ram(&s->sram[1], OBJECT(s), "sec.sram",
+ sc->sram_size[1], &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
}
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
- &s->secsram);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
+ &s->sram[1]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -494,7 +496,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size[0] = 0xc0000;
- sc->secsram_size = 0x40000; /* 256 * KiB */
+ sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
sc->wdts_num = 4;
@@ -522,7 +524,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1060_A2_SILICON_REV;
sc->sram_size[0] = 0xc0000;
- sc->secsram_size = 0x40000; /* 256 * KiB */
+ sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
sc->spis_num = 2;
sc->wdts_num = 4;
sc->uarts_num = 1;
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 10/37] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (8 preceding siblings ...)
2026-05-26 8:18 ` [PULL 09/37] hw/arm/aspeed: Consolidate secure SRAM into SRAM array Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 11/37] hw/arm/aspeed: Introduce AST1040 A0 SoC model Cédric Le Goater
` (27 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Add the AST1040 A0 silicon revision definition and register it
in the supported Aspeed silicon revision table.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-6-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/misc/aspeed_scu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index d003955428a5..c30940ab7683 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -46,6 +46,7 @@ struct AspeedSCUState {
#define AST2600_A3_SILICON_REV 0x05030303U
#define AST1030_A1_SILICON_REV 0x80010000U
#define AST1060_A2_SILICON_REV 0xA0030000U
+#define AST1040_A0_SILICON_REV 0x81000000U
#define AST2700_A1_SILICON_REV 0x06010103U
#define AST2700_A2_SILICON_REV 0x06020103U
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 9d9f43e6b563..c9b73a114805 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -562,6 +562,7 @@ static uint32_t aspeed_silicon_revs[] = {
AST1060_A2_SILICON_REV,
AST2700_A1_SILICON_REV,
AST2700_A2_SILICON_REV,
+ AST1040_A0_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 11/37] hw/arm/aspeed: Introduce AST1040 A0 SoC model
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (9 preceding siblings ...)
2026-05-26 8:18 ` [PULL 10/37] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 12/37] hw/arm/aspeed: Add AST1040 EVB machine model Cédric Le Goater
` (26 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
The AST1040 is based on an ARM Cortex-M4F CPU core. Since QEMU
currently does not provide Cortex-M4F support, use the existing
Cortex-M4 CPU model as a temporary replacement.
This initial implementation provides the basic infrastructure
required to boot firmware and run a minimal firmware shell,
including:
- ARM Cortex-M4 CPU integration
- NVIC interrupt controller support
- Internal HyperRAM and SRAM memory regions
- SCU integration
- UART devices and interrupt wiring
AST1040 SCU behavior is compatible with the AST2700 SCUIO model,
so reuse the existing AST2700 SCUIO implementation directly
instead of introducing another identical SCU model. This reduces
duplicate code and helps minimize long-term codebase maintenance.
Several peripherals are currently modeled as unimplemented
devices and can be added incrementally in future updates.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast1040.c | 254 ++++++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 3 +-
2 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast1040.c
diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
new file mode 100644
index 000000000000..8efcdad8f6a0
--- /dev/null
+++ b/hw/arm/aspeed_ast1040.c
@@ -0,0 +1,254 @@
+/*
+ * ASPEED AST1040 SoC
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "system/address-spaces.h"
+#include "system/system.h"
+#include "hw/core/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+
+static const hwaddr aspeed_soc_ast1040_memmap[] = {
+ [ASPEED_DEV_SRAM1] = 0x00000000, /* Hyper RAM */
+ [ASPEED_DEV_FMC] = 0x74000000,
+ [ASPEED_DEV_SPI0] = 0x74010000,
+ [ASPEED_DEV_SPI1] = 0x74020000,
+ [ASPEED_DEV_PWM] = 0x740C0000,
+ [ASPEED_DEV_UDC] = 0x74120000,
+ [ASPEED_DEV_SRAM0] = 0x74B80000,
+ [ASPEED_DEV_ADC] = 0x74C00000,
+ [ASPEED_DEV_JTAG0] = 0x74C01000,
+ [ASPEED_DEV_SCU] = 0x74C02000,
+ [ASPEED_DEV_ESPI] = 0x74C05000,
+ [ASPEED_DEV_JTAG1] = 0x74C09000,
+ [ASPEED_DEV_GPIO] = 0x74C0B000,
+ [ASPEED_DEV_SGPIOM0] = 0x74C0C000,
+ [ASPEED_DEV_SGPIOM1] = 0x74C0D000,
+ [ASPEED_DEV_I2C] = 0x74C0F000,
+ [ASPEED_DEV_I3C] = 0x74C20000,
+ [ASPEED_DEV_UART0] = 0x74C33000,
+ [ASPEED_DEV_UART1] = 0x74C33100,
+ [ASPEED_DEV_UART2] = 0x74C33200,
+ [ASPEED_DEV_UART3] = 0x74C33300,
+ [ASPEED_DEV_UART4] = 0x74C33400,
+ [ASPEED_DEV_UART5] = 0x74C33500,
+ [ASPEED_DEV_UART6] = 0x74C33600,
+ [ASPEED_DEV_UART7] = 0x74C33700,
+ [ASPEED_DEV_UART8] = 0x74C33800,
+ [ASPEED_DEV_UART9] = 0x74C33900,
+ [ASPEED_DEV_UART10] = 0x74C33A00,
+ [ASPEED_DEV_UART11] = 0x74C33B00,
+ [ASPEED_DEV_UART12] = 0x74C33C00,
+ [ASPEED_DEV_WDT] = 0x74C37000,
+ [ASPEED_DEV_TIMER1] = 0x74C3A000,
+};
+
+static const int aspeed_soc_ast1040_irqmap[] = {
+ [ASPEED_DEV_ESPI] = 10,
+ [ASPEED_DEV_I2C] = 64, /* 64 ~ 77 */
+ [ASPEED_DEV_ADC] = 80,
+ [ASPEED_DEV_GPIO] = 82,
+ [ASPEED_DEV_SGPIOM0] = 85,
+ [ASPEED_DEV_TIMER1] = 92,
+ [ASPEED_DEV_I3C] = 96, /* 96 ~ 103 */
+ [ASPEED_DEV_WDT] = 112,
+ [ASPEED_DEV_FMC] = 121,
+ [ASPEED_DEV_SPI0] = 122,
+ [ASPEED_DEV_SPI1] = 123,
+ [ASPEED_DEV_PWM] = 125,
+ [ASPEED_DEV_UART0] = 135,
+ [ASPEED_DEV_UART1] = 136,
+ [ASPEED_DEV_UART2] = 137,
+ [ASPEED_DEV_UART3] = 138,
+ [ASPEED_DEV_UART4] = 139,
+ [ASPEED_DEV_UART5] = 140,
+ [ASPEED_DEV_UART6] = 141,
+ [ASPEED_DEV_UART7] = 142,
+ [ASPEED_DEV_UART8] = 143,
+ [ASPEED_DEV_UART9] = 144,
+ [ASPEED_DEV_UART10] = 145,
+ [ASPEED_DEV_UART11] = 146,
+ [ASPEED_DEV_UART12] = 147,
+ [ASPEED_DEV_JTAG0] = 162,
+};
+
+static qemu_irq aspeed_soc_ast1040_get_irq(AspeedSoCState *s, int dev)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
+}
+
+static void aspeed_soc_ast1040_init(Object *obj)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ /* AST1040 uses the AST2700 SCUIO model */
+ object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCUIO);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "sgpiom[0]", &s->sgpiom[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "sgpiom[1]", &s->sgpiom[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "jtag[0]", &s->jtag[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "jtag[1]", &s->jtag[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
+static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ g_autofree char *hyperram_name = NULL;
+ g_autofree char *sram_name = NULL;
+ DeviceState *armv7m;
+ Error *err = NULL;
+ int uart;
+ int i;
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /* AST1040 CPU Core */
+ armv7m = DEVICE(&a->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 256);
+ qdev_prop_set_string(armv7m, "cpu-type",
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ object_property_set_link(OBJECT(&a->armv7m), "memory",
+ OBJECT(s->memory), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
+
+ /* Internal SRAM */
+ sram_name = g_strdup_printf("aspeed.sram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size[0], &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
+ &s->sram[0]);
+
+ /* Internal Hyper RAM */
+ hyperram_name = g_strdup_printf("aspeed.hyperram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+ memory_region_init_ram(&s->sram[1], OBJECT(s), hyperram_name,
+ sc->sram_size[1], &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
+ &s->sram[1]);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
+
+ /* UART */
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_ast1040_get_irq(s, uart));
+ }
+
+ /* Unimplemented peripherals */
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
+ "aspeed.pwm",
+ sc->memmap[ASPEED_DEV_PWM], 0x10000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi),
+ "aspeed.espi",
+ sc->memmap[ASPEED_DEV_ESPI], 0x1000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc),
+ "aspeed.udc",
+ sc->memmap[ASPEED_DEV_UDC], 0x4000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[0]),
+ "aspeed.sgpiom0",
+ sc->memmap[ASPEED_DEV_SGPIOM0], 0x1000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[1]),
+ "aspeed.sgpiom1",
+ sc->memmap[ASPEED_DEV_SGPIOM1], 0x1000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),
+ "aspeed.jtag0",
+ sc->memmap[ASPEED_DEV_JTAG0], 0x100);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),
+ "aspeed.jtag1",
+ sc->memmap[ASPEED_DEV_JTAG1], 0x100);
+}
+
+static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast1040_realize;
+
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST1040_A0_SILICON_REV;
+ sc->sram_size[0] = 128 * KiB;
+ sc->sram_size[1] = 16 * MiB; /* Hyper RAM */
+ sc->uarts_num = 13;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast1040_irqmap;
+ sc->memmap = aspeed_soc_ast1040_memmap;
+ sc->num_cpus = 1;
+}
+
+static const TypeInfo aspeed_soc_ast1040_types[] = {
+ {
+ .name = "ast1040-a0",
+ .parent = TYPE_ASPEED10X0_SOC,
+ .instance_init = aspeed_soc_ast1040_init,
+ .class_init = aspeed_soc_ast1040_class_init,
+ }
+};
+
+DEFINE_TYPES(aspeed_soc_ast1040_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 4fe7efd189e2..1da08d198bee 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -63,7 +63,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_gb200nvl.c',
'aspeed_ast2600_rainier.c',
'aspeed_ast10x0.c',
- 'aspeed_ast10x0_evb.c'))
+ 'aspeed_ast10x0_evb.c',
+ 'aspeed_ast1040.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast1700.c',
'aspeed_ast27x0.c',
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 12/37] hw/arm/aspeed: Add AST1040 EVB machine model
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (10 preceding siblings ...)
2026-05-26 8:18 ` [PULL 11/37] hw/arm/aspeed: Introduce AST1040 A0 SoC model Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 13/37] tests/function/aspeed: Add AST1040 functional test Cédric Le Goater
` (25 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
AST1040 is the next-generation device following AST1030 and is
primarily designed as a bridge/BIC controller platform. Introduce
a dedicated AST1040 EVB machine implementation for firmware
development and validation.
Although the existing ast10x0 EVB machine code already provides
a reusable minibmc initialization flow, AST1040 requires
different platform settings, including:
- Different SYSCLK frequency
- Different internal flash size
To avoid overloading the existing AST1030-specific helper,
introduce a separate aspeed_bic_machine_init() implementation in
a dedicated source file.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-8-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast1040_evb.c | 73 +++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 3 +-
2 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast1040_evb.c
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
new file mode 100644
index 000000000000..1d9b55247f07
--- /dev/null
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -0,0 +1,73 @@
+/*
+ * ASPEED AST1040 EVB
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/core/qdev-clock.h"
+#include "system/system.h"
+
+#define AST1040_INTERNAL_FLASH_SIZE (4 * MiB)
+/* Main SYSCLK frequency in Hz (400MHz) */
+#define SYSCLK_FRQ 400000000ULL
+
+static void aspeed_bic_machine_init(MachineState *machine)
+{
+ AspeedMachineState *bmc = ASPEED_MACHINE(machine);
+ AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
+ Clock *sysclk;
+
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
+
+ object_property_set_link(OBJECT(bmc->soc), "memory",
+ OBJECT(get_system_memory()), &error_abort);
+ aspeed_connect_serial_hds_to_uarts(bmc);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu),
+ machine->kernel_filename,
+ 0,
+ AST1040_INTERNAL_FLASH_SIZE);
+}
+
+static void aspeed_machine_ast1040_evb_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST1040 BIC EVB (Cortex-M4F)";
+ amc->soc_name = "ast1040-a0";
+ amc->hw_strap1 = 0;
+ amc->hw_strap2 = 0;
+ mc->init = aspeed_bic_machine_init;
+ mc->default_ram_size = 0;
+ amc->macs_mask = 0;
+ amc->uart_default = ASPEED_DEV_UART12;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast1040_evb_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast1040-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast1040_evb_class_init,
+ .interfaces = arm_machine_interfaces,
+ }
+};
+
+DEFINE_TYPES(aspeed_ast1040_evb_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 1da08d198bee..68d204bb4ebf 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -64,7 +64,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_rainier.c',
'aspeed_ast10x0.c',
'aspeed_ast10x0_evb.c',
- 'aspeed_ast1040.c'))
+ 'aspeed_ast1040.c',
+ 'aspeed_ast1040_evb.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast1700.c',
'aspeed_ast27x0.c',
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 13/37] tests/function/aspeed: Add AST1040 functional test
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (11 preceding siblings ...)
2026-05-26 8:18 ` [PULL 12/37] hw/arm/aspeed: Add AST1040 EVB machine model Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 14/37] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board Cédric Le Goater
` (24 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Add a new functional test for the ast1040-evb machine to
validate Zephyr firmware boot flow in QEMU.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-9-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/functional/arm/meson.build | 1 +
tests/functional/arm/test_aspeed_ast1040.py | 35 +++++++++++++++++++++
2 files changed, 36 insertions(+)
create mode 100644 tests/functional/arm/test_aspeed_ast1040.py
diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.build
index 959179a56f6d..61b00932db93 100644
--- a/tests/functional/arm/meson.build
+++ b/tests/functional/arm/meson.build
@@ -34,6 +34,7 @@ tests_arm_system_quick = [
tests_arm_system_thorough = [
'aspeed_ast1030',
+ 'aspeed_ast1040',
'aspeed_ast1060',
'aspeed_palmetto',
'aspeed_romulus',
diff --git a/tests/functional/arm/test_aspeed_ast1040.py b/tests/functional/arm/test_aspeed_ast1040.py
new file mode 100644
index 000000000000..e4d8ecb37a58
--- /dev/null
+++ b/tests/functional/arm/test_aspeed_ast1040.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED SoCs with firmware
+#
+# Copyright (C) 2026 ASPEED Technology Inc
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from aspeed import AspeedTest
+from qemu_test import Asset, exec_command_and_wait_for_pattern
+
+
+class AST1040Machine(AspeedTest):
+
+ ASSET_ZEPHYR_3_07 = Asset(
+ ('https://github.com/AspeedTech-BMC'
+ '/zephyr/releases/download/v00.03.07/ast1040-evb-demo.zip'),
+ 'b5189797c22c2d732ddc27670c1efdeba821a2747c9c7434f190791125baa121')
+
+ def test_arm_ast1040_zephyros(self):
+ self.set_machine('ast1040-evb')
+
+ kernel_name = "zephyr.bin"
+ kernel_file = self.archive_extract(
+ self.ASSET_ZEPHYR_3_07, member=kernel_name)
+
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_file, '-nographic')
+ self.vm.launch()
+ self.wait_for_console_pattern("uart:~$")
+ exec_command_and_wait_for_pattern(self, "help",
+ "Available commands")
+
+if __name__ == '__main__':
+ AspeedTest.main()
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 14/37] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (12 preceding siblings ...)
2026-05-26 8:18 ` [PULL 13/37] tests/function/aspeed: Add AST1040 functional test Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 15/37] hw/misc/aspeed_pwm: convert to use Resettable interface Cédric Le Goater
` (23 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Update the Aspeed AST10x0 documentation to include the
AST1040 evaluation board and clarify the AST10x0 family
classification.
The documentation now describes:
- AST1030 and AST1040 as Bridge IC devices
- AST1060 as a Platform Root of Trust processor
- AST1040 Cortex-M4F CPU frequency running at 400 MHz
Also add the ast1040-evb machine entry to the supported
AST10x0 SoC based machine list.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
docs/system/arm/aspeed.rst | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index a2eccf54892d..2d51ceeb8443 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -441,18 +441,26 @@ Use ``tio`` or another terminal emulator to connect to the consoles:
$ tio /dev/pts/57
-Aspeed MiniBMC and Platform Root of Trust processor family boards (``ast1030-evb``, ``ast1060-evb``)
-====================================================================================================
+Aspeed Bridge IC and Platform Root of Trust processor family boards (``ast1030-evb``, ``ast1040-evb``, ``ast1060-evb``)
+=======================================================================================================================
-The QEMU Aspeed machines model mini BMCs and Platform Root of Trust processors of various Aspeed
-evaluation boards. They are based on different releases of the Aspeed SoC : the AST1030 (MiniBMC)
-and AST1060 (Platform Root of Trust Processor), both integrating an Arm Cortex M4F CPU (200MHz).
+The QEMU Aspeed machines model Bridge ICs and Platform Root of Trust processors
+of various Aspeed evaluation boards. They are based on different members of
+the Aspeed AST10x0 SoC family:
+
+- AST1030 : Bridge IC
+- AST1040 : Bridge IC
+- AST1060 : Platform Root of Trust processor
+
+The AST1030 and AST1060 integrate an Arm Cortex-M4F CPU running at 200 MHz.
+The AST1040 integrates an Arm Cortex-M4F CPU running at 400 MHz.
The SoC comes with SRAM, SPI, I2C, etc.
AST10x0 SoC based machines :
- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F)
+- ``ast1040-evb`` Aspeed AST1040 Evaluation board (Cortex-M4F)
- ``ast1060-evb`` Aspeed AST1060 Evaluation board (Cortex-M4F)
Supported devices
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 15/37] hw/misc/aspeed_pwm: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (13 preceding siblings ...)
2026-05-26 8:18 ` [PULL 14/37] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 16/37] hw/misc/aspeed_peci: " Cédric Le Goater
` (22 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-2-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_pwm.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c
index ee3d5884be22..673a0f1346f0 100644
--- a/hw/misc/aspeed_pwm.c
+++ b/hw/misc/aspeed_pwm.c
@@ -65,9 +65,9 @@ static const MemoryRegionOps aspeed_pwm_ops = {
},
};
-static void aspeed_pwm_reset(DeviceState *dev)
+static void aspeed_pwm_reset_hold(Object *obj, ResetType type)
{
- struct AspeedPWMState *s = ASPEED_PWM(dev);
+ AspeedPWMState *s = ASPEED_PWM(obj);
memset(s->regs, 0, sizeof(s->regs));
}
@@ -98,9 +98,10 @@ static const VMStateDescription vmstate_aspeed_pwm = {
static void aspeed_pwm_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_pwm_realize;
- device_class_set_legacy_reset(dc, aspeed_pwm_reset);
+ rc->phases.hold = aspeed_pwm_reset_hold;
dc->desc = "Aspeed PWM Controller";
dc->vmsd = &vmstate_aspeed_pwm;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 16/37] hw/misc/aspeed_peci: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (14 preceding siblings ...)
2026-05-26 8:18 ` [PULL 15/37] hw/misc/aspeed_pwm: convert to use Resettable interface Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 17/37] hw/misc/aspeed_hace: " Cédric Le Goater
` (21 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-3-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_peci.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_peci.c b/hw/misc/aspeed_peci.c
index 0569ee57d1fa..7469f82fad19 100644
--- a/hw/misc/aspeed_peci.c
+++ b/hw/misc/aspeed_peci.c
@@ -123,9 +123,9 @@ static void aspeed_peci_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->irq);
}
-static void aspeed_peci_reset(DeviceState *dev)
+static void aspeed_peci_reset_hold(Object *obj, ResetType type)
{
- AspeedPECIState *s = ASPEED_PECI(dev);
+ AspeedPECIState *s = ASPEED_PECI(obj);
memset(s->regs, 0, sizeof(s->regs));
}
@@ -133,9 +133,10 @@ static void aspeed_peci_reset(DeviceState *dev)
static void aspeed_peci_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_peci_realize;
- device_class_set_legacy_reset(dc, aspeed_peci_reset);
+ rc->phases.hold = aspeed_peci_reset_hold;
dc->desc = "Aspeed PECI Controller";
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 17/37] hw/misc/aspeed_hace: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (15 preceding siblings ...)
2026-05-26 8:18 ` [PULL 16/37] hw/misc/aspeed_peci: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 18/37] hw/misc/aspeed_sbc: " Cédric Le Goater
` (20 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-4-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_hace.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index a322905cb37b..4c9e913f6c66 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -624,9 +624,9 @@ static const MemoryRegionOps aspeed_hace_ops = {
},
};
-static void aspeed_hace_reset(DeviceState *dev)
+static void aspeed_hace_reset_hold(Object *obj, ResetType type)
{
- struct AspeedHACEState *s = ASPEED_HACE(dev);
+ AspeedHACEState *s = ASPEED_HACE(obj);
AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
if (s->hash_ctx != NULL) {
@@ -687,10 +687,11 @@ static void aspeed_hace_unrealize(DeviceState *dev)
static void aspeed_hace_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_hace_realize;
dc->unrealize = aspeed_hace_unrealize;
- device_class_set_legacy_reset(dc, aspeed_hace_reset);
+ rc->phases.hold = aspeed_hace_reset_hold;
device_class_set_props(dc, aspeed_hace_properties);
dc->vmsd = &vmstate_aspeed_hace;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 18/37] hw/misc/aspeed_sbc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (16 preceding siblings ...)
2026-05-26 8:18 ` [PULL 17/37] hw/misc/aspeed_hace: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 19/37] hw/misc/aspeed_xdma: " Cédric Le Goater
` (19 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-5-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_sbc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index e5dab1c7bb7c..6125d2f134e8 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -261,9 +261,9 @@ static const MemoryRegionOps aspeed_sbc_ops = {
},
};
-static void aspeed_sbc_reset(DeviceState *dev)
+static void aspeed_sbc_reset_hold(Object *obj, ResetType type)
{
- struct AspeedSBCState *s = ASPEED_SBC(dev);
+ AspeedSBCState *s = ASPEED_SBC(obj);
memset(s->regs, 0, sizeof(s->regs));
@@ -330,9 +330,10 @@ static const Property aspeed_sbc_properties[] = {
static void aspeed_sbc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_sbc_realize;
- device_class_set_legacy_reset(dc, aspeed_sbc_reset);
+ rc->phases.hold = aspeed_sbc_reset_hold;
dc->vmsd = &vmstate_aspeed_sbc;
device_class_set_props(dc, aspeed_sbc_properties);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 19/37] hw/misc/aspeed_xdma: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (17 preceding siblings ...)
2026-05-26 8:18 ` [PULL 18/37] hw/misc/aspeed_sbc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 20/37] hw/misc/aspeed_lpc: " Cédric Le Goater
` (18 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-6-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_xdma.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c
index 3e2beafcedfb..80b32593336c 100644
--- a/hw/misc/aspeed_xdma.c
+++ b/hw/misc/aspeed_xdma.c
@@ -129,9 +129,9 @@ static void aspeed_xdma_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &xdma->iomem);
}
-static void aspeed_xdma_reset(DeviceState *dev)
+static void aspeed_xdma_reset_hold(Object *obj, ResetType type)
{
- AspeedXDMAState *xdma = ASPEED_XDMA(dev);
+ AspeedXDMAState *xdma = ASPEED_XDMA(obj);
AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma);
xdma->bmc_cmdq_readp_set = 0;
@@ -220,9 +220,10 @@ static const TypeInfo aspeed_2400_xdma_info = {
static void aspeed_xdma_class_init(ObjectClass *classp, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(classp);
+ ResettableClass *rc = RESETTABLE_CLASS(classp);
dc->realize = aspeed_xdma_realize;
- device_class_set_legacy_reset(dc, aspeed_xdma_reset);
+ rc->phases.hold = aspeed_xdma_reset_hold;
dc->vmsd = &aspeed_xdma_vmstate;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 20/37] hw/misc/aspeed_lpc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (18 preceding siblings ...)
2026-05-26 8:18 ` [PULL 19/37] hw/misc/aspeed_xdma: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 21/37] hw/misc/aspeed_sdmc: " Cédric Le Goater
` (17 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-7-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_lpc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c
index 68f0f6334bc3..f69c48da125c 100644
--- a/hw/misc/aspeed_lpc.c
+++ b/hw/misc/aspeed_lpc.c
@@ -384,9 +384,9 @@ static const MemoryRegionOps aspeed_lpc_ops = {
},
};
-static void aspeed_lpc_reset(DeviceState *dev)
+static void aspeed_lpc_reset_hold(Object *obj, ResetType type)
{
- struct AspeedLPCState *s = ASPEED_LPC(dev);
+ AspeedLPCState *s = ASPEED_LPC(obj);
s->subdevice_irqs_pending = 0;
@@ -461,9 +461,10 @@ static const Property aspeed_lpc_properties[] = {
static void aspeed_lpc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_lpc_realize;
- device_class_set_legacy_reset(dc, aspeed_lpc_reset);
+ rc->phases.hold = aspeed_lpc_reset_hold;
dc->desc = "Aspeed LPC Controller",
dc->vmsd = &vmstate_aspeed_lpc;
device_class_set_props(dc, aspeed_lpc_properties);
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 21/37] hw/misc/aspeed_sdmc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (19 preceding siblings ...)
2026-05-26 8:18 ` [PULL 20/37] hw/misc/aspeed_lpc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 22/37] hw/misc/aspeed_scu: " Cédric Le Goater
` (16 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-8-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_sdmc.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 59b4a9a42647..055abf7f50f0 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -199,9 +199,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
.valid.max_access_size = 4,
};
-static void aspeed_sdmc_reset(DeviceState *dev)
+static void aspeed_sdmc_reset_hold(Object *obj, ResetType type)
{
- AspeedSDMCState *s = ASPEED_SDMC(dev);
+ AspeedSDMCState *s = ASPEED_SDMC(obj);
AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
memset(s->regs, 0, sizeof(s->regs));
@@ -302,8 +302,9 @@ static const Property aspeed_sdmc_properties[] = {
static void aspeed_sdmc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_sdmc_realize;
- device_class_set_legacy_reset(dc, aspeed_sdmc_reset);
+ rc->phases.hold = aspeed_sdmc_reset_hold;
dc->desc = "ASPEED SDRAM Memory Controller";
dc->vmsd = &vmstate_aspeed_sdmc;
device_class_set_props(dc, aspeed_sdmc_properties);
@@ -560,9 +561,9 @@ static const TypeInfo aspeed_2600_sdmc_info = {
.class_init = aspeed_2600_sdmc_class_init,
};
-static void aspeed_2700_sdmc_reset(DeviceState *dev)
+static void aspeed_2700_sdmc_reset_hold(Object *obj, ResetType type)
{
- AspeedSDMCState *s = ASPEED_SDMC(dev);
+ AspeedSDMCState *s = ASPEED_SDMC(obj);
AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
memset(s->regs, 0, sizeof(s->regs));
@@ -676,10 +677,11 @@ static const uint64_t
static void aspeed_2700_sdmc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
dc->desc = "ASPEED 2700 SDRAM Memory Controller";
- device_class_set_legacy_reset(dc, aspeed_2700_sdmc_reset);
+ rc->phases.hold = aspeed_2700_sdmc_reset_hold;
asc->is_bus64bit = true;
asc->max_ram_size = 8 * GiB;
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 22/37] hw/misc/aspeed_scu: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (20 preceding siblings ...)
2026-05-26 8:18 ` [PULL 21/37] hw/misc/aspeed_sdmc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 23/37] hw/misc/aspeed_ltpi: " Cédric Le Goater
` (15 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-9-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_scu.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index c9b73a114805..19da6c075fae 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -542,10 +542,10 @@ static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
return clkin * multiplier;
}
-static void aspeed_scu_reset(DeviceState *dev)
+static void aspeed_scu_reset_hold(Object *obj, ResetType type)
{
- AspeedSCUState *s = ASPEED_SCU(dev);
- AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+ AspeedSCUState *s = ASPEED_SCU(obj);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[SILICON_REV] = s->silicon_rev;
@@ -616,8 +616,9 @@ static const Property aspeed_scu_properties[] = {
static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_scu_realize;
- device_class_set_legacy_reset(dc, aspeed_scu_reset);
+ rc->phases.hold = aspeed_scu_reset_hold;
dc->desc = "ASPEED System Control Unit";
dc->vmsd = &vmstate_aspeed_scu;
device_class_set_props(dc, aspeed_scu_properties);
@@ -822,10 +823,10 @@ static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
[AST2600_CHIP_ID1] = 0x88884444,
};
-static void aspeed_ast2600_scu_reset(DeviceState *dev)
+static void aspeed_ast2600_scu_reset_hold(Object *obj, ResetType type)
{
- AspeedSCUState *s = ASPEED_SCU(dev);
- AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+ AspeedSCUState *s = ASPEED_SCU(obj);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
@@ -844,10 +845,11 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev)
static void aspeed_2600_scu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
dc->desc = "ASPEED 2600 System Control Unit";
- device_class_set_legacy_reset(dc, aspeed_ast2600_scu_reset);
+ rc->phases.hold = aspeed_ast2600_scu_reset_hold;
asc->resets = ast2600_a3_resets;
asc->calc_hpll = aspeed_2600_scu_calc_hpll;
asc->get_apb = aspeed_2600_scu_get_apb_freq;
@@ -950,10 +952,10 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_VGA_SCRATCH_0] = 0x00000040,
};
-static void aspeed_ast2700_scu_reset(DeviceState *dev)
+static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
{
- AspeedSCUState *s = ASPEED_SCU(dev);
- AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+ AspeedSCUState *s = ASPEED_SCU(obj);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[AST2700_SILICON_REV] = s->silicon_rev;
@@ -963,10 +965,11 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
dc->desc = "ASPEED 2700 System Control Unit";
- device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset);
+ rc->phases.hold = aspeed_ast2700_scu_reset_hold;
asc->resets = ast2700_a0_resets;
asc->calc_hpll = aspeed_2600_scu_calc_hpll;
asc->get_apb = aspeed_2700_scu_get_apb_freq;
@@ -1082,10 +1085,11 @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
dc->desc = "ASPEED 2700 System Control Unit I/O";
- device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset);
+ rc->phases.hold = aspeed_ast2700_scu_reset_hold;
asc->resets = ast2700_a0_resets_io;
asc->calc_hpll = aspeed_2600_scu_calc_hpll;
asc->get_apb = aspeed_2700_scuio_get_apb_freq;
@@ -1123,10 +1127,10 @@ static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
[AST2600_CHIP_ID1] = 0x0BADCAFE,
};
-static void aspeed_ast1030_scu_reset(DeviceState *dev)
+static void aspeed_ast1030_scu_reset_hold(Object *obj, ResetType type)
{
- AspeedSCUState *s = ASPEED_SCU(dev);
- AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+ AspeedSCUState *s = ASPEED_SCU(obj);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
@@ -1140,10 +1144,11 @@ static void aspeed_ast1030_scu_reset(DeviceState *dev)
static void aspeed_1030_scu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
dc->desc = "ASPEED 1030 System Control Unit";
- device_class_set_legacy_reset(dc, aspeed_ast1030_scu_reset);
+ rc->phases.hold = aspeed_ast1030_scu_reset_hold;
asc->resets = ast1030_a1_resets;
asc->calc_hpll = aspeed_2600_scu_calc_hpll;
asc->get_apb = aspeed_1030_scu_get_apb_freq;
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 23/37] hw/misc/aspeed_ltpi: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (21 preceding siblings ...)
2026-05-26 8:18 ` [PULL 22/37] hw/misc/aspeed_scu: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 24/37] hw/pci-host/aspeed_pcie: " Cédric Le Goater
` (14 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-10-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/misc/aspeed_ltpi.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c
index 131cea9c6b8b..956e91d14361 100644
--- a/hw/misc/aspeed_ltpi.c
+++ b/hw/misc/aspeed_ltpi.c
@@ -112,9 +112,9 @@ static const MemoryRegionOps aspeed_ltpi_ctrl_ops = {
},
};
-static void aspeed_ltpi_reset(DeviceState *dev)
+static void aspeed_ltpi_reset_hold(Object *obj, ResetType type)
{
- AspeedLTPIState *s = ASPEED_LTPI(dev);
+ AspeedLTPIState *s = ASPEED_LTPI(obj);
memset(s->ctrl_regs, 0, sizeof(s->ctrl_regs));
memset(s->phy_regs, 0, sizeof(s->phy_regs));
@@ -173,9 +173,10 @@ static void aspeed_ltpi_realize(DeviceState *dev, Error **errp)
static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_ltpi_realize;
dc->vmsd = &vmstate_aspeed_ltpi;
- device_class_set_legacy_reset(dc, aspeed_ltpi_reset);
+ rc->phases.hold = aspeed_ltpi_reset_hold;
}
static const TypeInfo aspeed_ltpi_info = {
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 24/37] hw/pci-host/aspeed_pcie: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (22 preceding siblings ...)
2026-05-26 8:18 ` [PULL 23/37] hw/misc/aspeed_ltpi: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 25/37] hw/timer/aspeed_timer: " Cédric Le Goater
` (13 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-11-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/pci-host/aspeed_pcie.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index c150496f7b9c..186e5aeea298 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -613,9 +613,9 @@ static void aspeed_pcie_cfg_instance_init(Object *obj)
return;
}
-static void aspeed_pcie_cfg_reset(DeviceState *dev)
+static void aspeed_pcie_cfg_reset_hold(Object *obj, ResetType type)
{
- AspeedPCIECfgState *s = ASPEED_PCIE_CFG(dev);
+ AspeedPCIECfgState *s = ASPEED_PCIE_CFG(obj);
AspeedPCIECfgClass *apc = ASPEED_PCIE_CFG_GET_CLASS(s);
memset(s->regs, 0, apc->nr_regs << 2);
@@ -663,12 +663,13 @@ static const Property aspeed_pcie_cfg_props[] = {
static void aspeed_pcie_cfg_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedPCIECfgClass *apc = ASPEED_PCIE_CFG_CLASS(klass);
dc->desc = "ASPEED PCIe Config";
dc->realize = aspeed_pcie_cfg_realize;
dc->unrealize = aspeed_pcie_cfg_unrealize;
- device_class_set_legacy_reset(dc, aspeed_pcie_cfg_reset);
+ rc->phases.hold = aspeed_pcie_cfg_reset_hold;
device_class_set_props(dc, aspeed_pcie_cfg_props);
apc->reg_ops = &aspeed_pcie_cfg_ops;
@@ -870,9 +871,9 @@ static const MemoryRegionOps aspeed_pcie_phy_ops = {
},
};
-static void aspeed_pcie_phy_reset(DeviceState *dev)
+static void aspeed_pcie_phy_reset_hold(Object *obj, ResetType type)
{
- AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(dev);
+ AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(obj);
AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_GET_CLASS(s);
memset(s->regs, 0, apc->nr_regs << 2);
@@ -913,12 +914,13 @@ static const Property aspeed_pcie_phy_props[] = {
static void aspeed_pcie_phy_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_CLASS(klass);
dc->desc = "ASPEED PCIe Phy";
dc->realize = aspeed_pcie_phy_realize;
dc->unrealize = aspeed_pcie_phy_unrealize;
- device_class_set_legacy_reset(dc, aspeed_pcie_phy_reset);
+ rc->phases.hold = aspeed_pcie_phy_reset_hold;
device_class_set_props(dc, aspeed_pcie_phy_props);
apc->nr_regs = 0x100 >> 2;
@@ -932,9 +934,9 @@ static const TypeInfo aspeed_pcie_phy_info = {
.class_size = sizeof(AspeedPCIEPhyClass),
};
-static void aspeed_2700_pcie_phy_reset(DeviceState *dev)
+static void aspeed_2700_pcie_phy_reset_hold(Object *obj, ResetType type)
{
- AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(dev);
+ AspeedPCIEPhyState *s = ASPEED_PCIE_PHY(obj);
AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_GET_CLASS(s);
memset(s->regs, 0, apc->nr_regs << 2);
@@ -950,10 +952,11 @@ static void aspeed_2700_pcie_phy_class_init(ObjectClass *klass,
const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedPCIEPhyClass *apc = ASPEED_PCIE_PHY_CLASS(klass);
dc->desc = "ASPEED AST2700 PCIe Phy";
- device_class_set_legacy_reset(dc, aspeed_2700_pcie_phy_reset);
+ rc->phases.hold = aspeed_2700_pcie_phy_reset_hold;
apc->nr_regs = 0x800 >> 2;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 25/37] hw/timer/aspeed_timer: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (23 preceding siblings ...)
2026-05-26 8:18 ` [PULL 24/37] hw/pci-host/aspeed_pcie: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 26/37] hw/gpio/aspeed_gpio: " Cédric Le Goater
` (12 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-12-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/timer/aspeed_timer.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 1e954f7aec5c..69f5c89215c5 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -834,10 +834,10 @@ static void aspeed_timer_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
}
-static void aspeed_timer_reset(DeviceState *dev)
+static void aspeed_timer_reset_hold(Object *obj, ResetType type)
{
int i;
- AspeedTimerCtrlState *s = ASPEED_TIMER(dev);
+ AspeedTimerCtrlState *s = ASPEED_TIMER(obj);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
AspeedTimer *t = &s->timers[i];
@@ -898,9 +898,10 @@ static const Property aspeed_timer_properties[] = {
static void timer_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_timer_realize;
- device_class_set_legacy_reset(dc, aspeed_timer_reset);
+ rc->phases.hold = aspeed_timer_reset_hold;
dc->desc = "ASPEED Timer";
dc->vmsd = &vmstate_aspeed_timer_state;
device_class_set_props(dc, aspeed_timer_properties);
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 26/37] hw/gpio/aspeed_gpio: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (24 preceding siblings ...)
2026-05-26 8:18 ` [PULL 25/37] hw/timer/aspeed_timer: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 27/37] hw/sd/aspeed_sdhci: " Cédric Le Goater
` (11 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-13-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/gpio/aspeed_gpio.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 7d0f87e90c39..ef321b738620 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -1430,9 +1430,9 @@ static const MemoryRegionOps aspeed_gpio_2700_ops = {
.valid.max_access_size = 4,
};
-static void aspeed_gpio_reset(DeviceState *dev)
+static void aspeed_gpio_reset_hold(Object *obj, ResetType type)
{
- AspeedGPIOState *s = ASPEED_GPIO(dev);
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
/* TODO: respect the reset tolerance registers */
memset(s->sets, 0, sizeof(s->sets));
@@ -1533,9 +1533,10 @@ static const VMStateDescription vmstate_aspeed_gpio = {
static void aspeed_gpio_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_gpio_realize;
- device_class_set_legacy_reset(dc, aspeed_gpio_reset);
+ rc->phases.hold = aspeed_gpio_reset_hold;
dc->desc = "Aspeed GPIO Controller";
dc->vmsd = &vmstate_aspeed_gpio;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 27/37] hw/sd/aspeed_sdhci: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (25 preceding siblings ...)
2026-05-26 8:18 ` [PULL 26/37] hw/gpio/aspeed_gpio: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 28/37] hw/ssi/aspeed_smc: " Cédric Le Goater
` (10 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-14-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/sd/aspeed_sdhci.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 6684f8221a35..d93093c4df97 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -182,9 +182,9 @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
}
}
-static void aspeed_sdhci_reset(DeviceState *dev)
+static void aspeed_sdhci_reset_hold(Object *obj, ResetType type)
{
- AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
+ AspeedSDHCIState *sdhci = ASPEED_SDHCI(obj);
memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
@@ -211,9 +211,10 @@ static const Property aspeed_sdhci_properties[] = {
static void aspeed_sdhci_class_init(ObjectClass *classp, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(classp);
+ ResettableClass *rc = RESETTABLE_CLASS(classp);
dc->realize = aspeed_sdhci_realize;
- device_class_set_legacy_reset(dc, aspeed_sdhci_reset);
+ rc->phases.hold = aspeed_sdhci_reset_hold;
dc->vmsd = &vmstate_aspeed_sdhci;
device_class_set_props(dc, aspeed_sdhci_properties);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 28/37] hw/ssi/aspeed_smc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (26 preceding siblings ...)
2026-05-26 8:18 ` [PULL 27/37] hw/sd/aspeed_sdhci: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 29/37] hw/intc/aspeed_vic: " Cédric Le Goater
` (9 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-15-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/ssi/aspeed_smc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index f0deeea996c3..3767ad0c7a3e 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -713,9 +713,9 @@ static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
}
}
-static void aspeed_smc_reset(DeviceState *d)
+static void aspeed_smc_reset_hold(Object *obj, ResetType type)
{
- AspeedSMCState *s = ASPEED_SMC(d);
+ AspeedSMCState *s = ASPEED_SMC(obj);
AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
int i;
@@ -1304,9 +1304,10 @@ static const Property aspeed_smc_properties[] = {
static void aspeed_smc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_smc_realize;
- device_class_set_legacy_reset(dc, aspeed_smc_reset);
+ rc->phases.hold = aspeed_smc_reset_hold;
device_class_set_props(dc, aspeed_smc_properties);
dc->vmsd = &vmstate_aspeed_smc;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 29/37] hw/intc/aspeed_vic: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (27 preceding siblings ...)
2026-05-26 8:18 ` [PULL 28/37] hw/ssi/aspeed_smc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 30/37] hw/intc/aspeed_intc: " Cédric Le Goater
` (8 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-16-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/intc/aspeed_vic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c
index b0a9a3970552..13d8423d835a 100644
--- a/hw/intc/aspeed_vic.c
+++ b/hw/intc/aspeed_vic.c
@@ -291,9 +291,9 @@ static const MemoryRegionOps aspeed_vic_ops = {
.valid.unaligned = false,
};
-static void aspeed_vic_reset(DeviceState *dev)
+static void aspeed_vic_reset_hold(Object *obj, ResetType type)
{
- AspeedVICState *s = ASPEED_VIC(dev);
+ AspeedVICState *s = ASPEED_VIC(obj);
s->level = 0;
s->raw = 0;
@@ -342,8 +342,9 @@ static const VMStateDescription vmstate_aspeed_vic = {
static void aspeed_vic_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_vic_realize;
- device_class_set_legacy_reset(dc, aspeed_vic_reset);
+ rc->phases.hold = aspeed_vic_reset_hold;
dc->desc = "ASPEED Interrupt Controller (New)";
dc->vmsd = &vmstate_aspeed_vic;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 30/37] hw/intc/aspeed_intc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (28 preceding siblings ...)
2026-05-26 8:18 ` [PULL 29/37] hw/intc/aspeed_vic: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 31/37] hw/i3c/aspeed_i3c: " Cédric Le Goater
` (7 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-17-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/intc/aspeed_intc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 52f2f946d59e..389280943091 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -692,9 +692,9 @@ static void aspeed_intc_instance_init(Object *obj)
}
}
-static void aspeed_intc_reset(DeviceState *dev)
+static void aspeed_intc_reset_hold(Object *obj, ResetType type)
{
- AspeedINTCState *s = ASPEED_INTC(dev);
+ AspeedINTCState *s = ASPEED_INTC(obj);
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
memset(s->regs, 0, aic->nr_regs << 2);
@@ -746,12 +746,13 @@ static void aspeed_intc_unrealize(DeviceState *dev)
static void aspeed_intc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED INTC Controller";
dc->realize = aspeed_intc_realize;
dc->unrealize = aspeed_intc_unrealize;
- device_class_set_legacy_reset(dc, aspeed_intc_reset);
+ rc->phases.hold = aspeed_intc_reset_hold;
dc->vmsd = NULL;
aic->reg_ops = &aspeed_intc_ops;
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 31/37] hw/i3c/aspeed_i3c: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (29 preceding siblings ...)
2026-05-26 8:18 ` [PULL 30/37] hw/intc/aspeed_intc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 32/37] hw/watchdog/wdt_aspeed: " Cédric Le Goater
` (6 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-18-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/i3c/aspeed_i3c.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index bac8c55bb091..de61d67dfdee 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c/aspeed_i3c.c
@@ -162,9 +162,9 @@ I3CBus *aspeed_i3c_get_bus(AspeedI3CState *s, uint8_t bus_num)
g_assert_not_reached();
}
-static void aspeed_i3c_reset(DeviceState *dev)
+static void aspeed_i3c_reset_hold(Object *obj, ResetType type)
{
- AspeedI3CState *s = ASPEED_I3C(dev);
+ AspeedI3CState *s = ASPEED_I3C(obj);
memset(s->regs, 0, sizeof(s->regs));
}
@@ -238,9 +238,10 @@ static const VMStateDescription vmstate_aspeed_i3c = {
static void aspeed_i3c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_i3c_realize;
- device_class_set_legacy_reset(dc, aspeed_i3c_reset);
+ rc->phases.hold = aspeed_i3c_reset_hold;
dc->desc = "Aspeed I3C Controller";
dc->vmsd = &vmstate_aspeed_i3c;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 32/37] hw/watchdog/wdt_aspeed: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (30 preceding siblings ...)
2026-05-26 8:18 ` [PULL 31/37] hw/i3c/aspeed_i3c: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 33/37] hw/net/ftgmac100: " Cédric Le Goater
` (5 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-19-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/watchdog/wdt_aspeed.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 26506f3c33f9..ae411593c583 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -247,9 +247,9 @@ static const MemoryRegionOps aspeed_wdt_ops = {
.valid.unaligned = false,
};
-static void aspeed_wdt_reset(DeviceState *dev)
+static void aspeed_wdt_reset_hold(Object *obj, ResetType type)
{
- AspeedWDTState *s = ASPEED_WDT(dev);
+ AspeedWDTState *s = ASPEED_WDT(obj);
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
s->regs[WDT_STATUS] = awc->default_status;
@@ -310,10 +310,11 @@ static const Property aspeed_wdt_properties[] = {
static void aspeed_wdt_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "ASPEED Watchdog Controller";
dc->realize = aspeed_wdt_realize;
- device_class_set_legacy_reset(dc, aspeed_wdt_reset);
+ rc->phases.hold = aspeed_wdt_reset_hold;
set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
dc->vmsd = &vmstate_aspeed_wdt;
device_class_set_props(dc, aspeed_wdt_properties);
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 33/37] hw/net/ftgmac100: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (31 preceding siblings ...)
2026-05-26 8:18 ` [PULL 32/37] hw/watchdog/wdt_aspeed: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 34/37] hw/fsi/aspeed_apb2opb: " Cédric Le Goater
` (4 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-20-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/net/ftgmac100.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index b3da48c343c7..2bec817b9dec 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -723,9 +723,9 @@ static void ftgmac100_do_reset(FTGMAC100State *s, bool sw_reset)
phy_reset(s);
}
-static void ftgmac100_reset(DeviceState *d)
+static void ftgmac100_reset_hold(Object *obj, ResetType type)
{
- ftgmac100_do_reset(FTGMAC100(d), false);
+ ftgmac100_do_reset(FTGMAC100(obj), false);
}
static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
@@ -1269,9 +1269,10 @@ static const Property ftgmac100_properties[] = {
static void ftgmac100_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &vmstate_ftgmac100;
- device_class_set_legacy_reset(dc, ftgmac100_reset);
+ rc->phases.hold = ftgmac100_reset_hold;
device_class_set_props(dc, ftgmac100_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->realize = ftgmac100_realize;
@@ -1387,9 +1388,9 @@ static const MemoryRegionOps aspeed_mii_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void aspeed_mii_reset(DeviceState *dev)
+static void aspeed_mii_reset_hold(Object *obj, ResetType type)
{
- AspeedMiiState *s = ASPEED_MII(dev);
+ AspeedMiiState *s = ASPEED_MII(obj);
s->phycr = 0;
s->phydata = 0;
@@ -1428,9 +1429,10 @@ static const Property aspeed_mii_properties[] = {
static void aspeed_mii_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &vmstate_aspeed_mii;
- device_class_set_legacy_reset(dc, aspeed_mii_reset);
+ rc->phases.hold = aspeed_mii_reset_hold;
dc->realize = aspeed_mii_realize;
dc->desc = "Aspeed MII controller";
device_class_set_props(dc, aspeed_mii_properties);
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 34/37] hw/fsi/aspeed_apb2opb: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (32 preceding siblings ...)
2026-05-26 8:18 ` [PULL 33/37] hw/net/ftgmac100: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 35/37] hw/rtc/aspeed_rtc: " Cédric Le Goater
` (3 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-21-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/fsi/aspeed_apb2opb.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/fsi/aspeed_apb2opb.c b/hw/fsi/aspeed_apb2opb.c
index 058abc86452d..f2d9a9669ada 100644
--- a/hw/fsi/aspeed_apb2opb.c
+++ b/hw/fsi/aspeed_apb2opb.c
@@ -302,9 +302,9 @@ static void fsi_aspeed_apb2opb_realize(DeviceState *dev, Error **errp)
}
}
-static void fsi_aspeed_apb2opb_reset(DeviceState *dev)
+static void fsi_aspeed_apb2opb_reset_hold(Object *obj, ResetType type)
{
- AspeedAPB2OPBState *s = ASPEED_APB2OPB(dev);
+ AspeedAPB2OPBState *s = ASPEED_APB2OPB(obj);
memcpy(s->regs, aspeed_apb2opb_reset, ASPEED_APB2OPB_NR_REGS);
}
@@ -312,10 +312,11 @@ static void fsi_aspeed_apb2opb_reset(DeviceState *dev)
static void fsi_aspeed_apb2opb_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "ASPEED APB2OPB Bridge";
dc->realize = fsi_aspeed_apb2opb_realize;
- device_class_set_legacy_reset(dc, fsi_aspeed_apb2opb_reset);
+ rc->phases.hold = fsi_aspeed_apb2opb_reset_hold;
}
static const TypeInfo aspeed_apb2opb_info = {
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 35/37] hw/rtc/aspeed_rtc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (33 preceding siblings ...)
2026-05-26 8:18 ` [PULL 34/37] hw/fsi/aspeed_apb2opb: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 36/37] hw/adc/aspeed_adc: " Cédric Le Goater
` (2 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-22-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/rtc/aspeed_rtc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index 6793e253f472..5245f3f95633 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -120,9 +120,9 @@ static void aspeed_rtc_write(void *opaque, hwaddr addr,
trace_aspeed_rtc_write(addr, val);
}
-static void aspeed_rtc_reset(DeviceState *d)
+static void aspeed_rtc_reset_hold(Object *obj, ResetType type)
{
- AspeedRtcState *rtc = ASPEED_RTC(d);
+ AspeedRtcState *rtc = ASPEED_RTC(obj);
rtc->offset = 0;
memset(rtc->reg, 0, sizeof(rtc->reg));
@@ -159,10 +159,11 @@ static void aspeed_rtc_realize(DeviceState *dev, Error **errp)
static void aspeed_rtc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_rtc_realize;
dc->vmsd = &vmstate_aspeed_rtc;
- device_class_set_legacy_reset(dc, aspeed_rtc_reset);
+ rc->phases.hold = aspeed_rtc_reset_hold;
}
static const TypeInfo aspeed_rtc_info = {
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 36/37] hw/adc/aspeed_adc: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (34 preceding siblings ...)
2026-05-26 8:18 ` [PULL 35/37] hw/rtc/aspeed_rtc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 8:18 ` [PULL 37/37] hw/i2c/aspeed_i2c: " Cédric Le Goater
2026-05-26 18:52 ` [PULL 00/37] aspeed queue Stefan Hajnoczi
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-23-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/adc/aspeed_adc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c
index 3cc75bbcd6e2..18b74898e16b 100644
--- a/hw/adc/aspeed_adc.c
+++ b/hw/adc/aspeed_adc.c
@@ -253,9 +253,9 @@ static const uint32_t aspeed_adc_resets[ASPEED_ADC_NR_REGS] = {
[CLOCK_CONTROL] = 0x0000000f,
};
-static void aspeed_adc_engine_reset(DeviceState *dev)
+static void aspeed_adc_engine_reset_hold(Object *obj, ResetType type)
{
- AspeedADCEngineState *s = ASPEED_ADC_ENGINE(dev);
+ AspeedADCEngineState *s = ASPEED_ADC_ENGINE(obj);
memcpy(s->regs, aspeed_adc_resets, sizeof(aspeed_adc_resets));
}
@@ -295,9 +295,10 @@ static const Property aspeed_adc_engine_properties[] = {
static void aspeed_adc_engine_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = aspeed_adc_engine_realize;
- device_class_set_legacy_reset(dc, aspeed_adc_engine_reset);
+ rc->phases.hold = aspeed_adc_engine_reset_hold;
device_class_set_props(dc, aspeed_adc_engine_properties);
dc->desc = "Aspeed Analog-to-Digital Engine";
dc->vmsd = &vmstate_aspeed_adc_engine;
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PULL 37/37] hw/i2c/aspeed_i2c: convert to use Resettable interface
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (35 preceding siblings ...)
2026-05-26 8:18 ` [PULL 36/37] hw/adc/aspeed_adc: " Cédric Le Goater
@ 2026-05-26 8:18 ` Cédric Le Goater
2026-05-26 18:52 ` [PULL 00/37] aspeed queue Stefan Hajnoczi
37 siblings, 0 replies; 39+ messages in thread
From: Cédric Le Goater @ 2026-05-26 8:18 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Kane Chen, Jamin Lin, Cédric Le Goater
From: Kane Chen <kane_chen@aspeedtech.com>
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.
Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-24-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/i2c/aspeed_i2c.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 90f83a03fd4f..80c445750059 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1160,9 +1160,9 @@ static const VMStateDescription aspeed_i2c_vmstate = {
}
};
-static void aspeed_i2c_reset(DeviceState *dev)
+static void aspeed_i2c_reset_hold(Object *obj, ResetType type)
{
- AspeedI2CState *s = ASPEED_I2C(dev);
+ AspeedI2CState *s = ASPEED_I2C(obj);
s->intr_status = 0;
}
@@ -1363,9 +1363,10 @@ static const Property aspeed_i2c_properties[] = {
static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->vmsd = &aspeed_i2c_vmstate;
- device_class_set_legacy_reset(dc, aspeed_i2c_reset);
+ rc->phases.hold = aspeed_i2c_reset_hold;
device_class_set_props(dc, aspeed_i2c_properties);
dc->realize = aspeed_i2c_realize;
dc->desc = "Aspeed I2C Controller";
@@ -1506,9 +1507,9 @@ static const TypeInfo aspeed_i2c_bus_slave_info = {
.class_init = aspeed_i2c_bus_slave_class_init,
};
-static void aspeed_i2c_bus_reset(DeviceState *dev)
+static void aspeed_i2c_bus_reset_hold(Object *obj, ResetType type)
{
- AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
+ AspeedI2CBus *s = ASPEED_I2C_BUS(obj);
memset(s->regs, 0, sizeof(s->regs));
s->pending_intr_sts = 0;
@@ -1556,10 +1557,11 @@ static const Property aspeed_i2c_bus_properties[] = {
static void aspeed_i2c_bus_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "Aspeed I2C Bus";
dc->realize = aspeed_i2c_bus_realize;
- device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset);
+ rc->phases.hold = aspeed_i2c_bus_reset_hold;
device_class_set_props(dc, aspeed_i2c_bus_properties);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PULL 00/37] aspeed queue
2026-05-26 8:18 [PULL 00/37] aspeed queue Cédric Le Goater
` (36 preceding siblings ...)
2026-05-26 8:18 ` [PULL 37/37] hw/i2c/aspeed_i2c: " Cédric Le Goater
@ 2026-05-26 18:52 ` Stefan Hajnoczi
37 siblings, 0 replies; 39+ messages in thread
From: Stefan Hajnoczi @ 2026-05-26 18:52 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-arm, qemu-devel, Cédric Le Goater
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 39+ messages in thread