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From: sashiko-bot@kernel.org
To: "Vishnu Reddy" <busanna.reddy@oss.qualcomm.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v8 05/12] media: iris: Enable Secure PAS support with IOMMU managed by Linux
Date: Wed, 10 Jun 2026 06:45:07 +0000	[thread overview]
Message-ID: <20260610064507.C548C1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260610-glymur-v8-5-1c79b9d51fc0@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Failure of `devm_qcom_scm_pas_context_alloc()` leaves an `ERR_PTR` in `core->pas_ctx`, causing a kernel panic on subsequent initialization attempts.
- [High] Missing `qcom_scm_pas_metadata_release()` causes a persistent DMA/tzmem memory leak.
--

commit 1775c14d01e8bdf8905d074121532c742ef2030a
Author: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>

media: iris: Enable Secure PAS support with IOMMU managed by Linux

This commit transitions the iris driver to support Secure Peripheral
Authentication Service (PAS) on platforms where Linux manages the IOMMU. It
creates a firmware context device, replaces qcom_mdt_load() with
qcom_mdt_pas_load(), and maps the IOMMU when a firmware device SID is present.

Link: https://lore.kernel.org/lkml/20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com/

> diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
> --- a/drivers/media/platform/qcom/iris/iris_firmware.c
> +++ b/drivers/media/platform/qcom/iris/iris_firmware.c
[ ... ]
> @@ -30,14 +33,21 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
>  	if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4)
>  		return -EINVAL;
>  
> -	ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
> +	ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res);
>  	if (ret)
>  		return ret;
>  
>  	mem_phys = res.start;
>  	res_size = resource_size(&res);
>  
> -	ret = request_firmware(&firmware, fw_name, dev);
> +	if (!core->pas_ctx) {
> +		core->pas_ctx = devm_qcom_scm_pas_context_alloc(core->dev, IRIS_PAS_ID,
> +								mem_phys, res_size);
> +		if (IS_ERR(core->pas_ctx))
> +			return PTR_ERR(core->pas_ctx);
> +	}
> +

[Severity: High]
If devm_qcom_scm_pas_context_alloc() fails, it returns an error pointer which
is directly assigned to core->pas_ctx. Since the context pointer is not
cleared back to NULL on failure, will subsequent initialization attempts
bypass the (!core->pas_ctx) check and illegally dereference the error pointer
further down in this function?

> +	ret = request_firmware(&firmware, fw_name, fw_dev);
>  	if (ret)
>  		return ret;
>  
[ ... ]
> @@ -53,9 +63,23 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
>  		goto err_release_fw;
>  	}
>  
> -	ret = qcom_mdt_load(dev, firmware, fw_name,
> -			    IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL);
> +	core->pas_ctx->use_tzmem = !!core->fw_dev;
> +	ret = qcom_mdt_pas_load(core->pas_ctx, firmware, fw_name, mem_virt, NULL);

[Severity: High]
This patch transitions to using qcom_mdt_pas_load(), which allocates a
metadata buffer and stores it in core->pas_ctx->ptr. Does this code leak
the metadata buffer by omitting the required qcom_scm_pas_metadata_release()
call in the error paths of this function, as well as during the teardown
sequence?

> +	if (ret)
> +		goto err_mem_unmap;
> +
[ ... ]
> @@ -100,7 +148,11 @@ int iris_fw_unload(struct iris_core *core)
>  {
> -	return qcom_scm_pas_shutdown(IRIS_PAS_ID);
> +	int ret;
> +
> +	ret = qcom_scm_pas_shutdown(core->pas_ctx->pas_id);
> +	iris_fw_iommu_unmap(core);
> +
> +	return ret;
>  }

[Severity: High]
Can memory exhaustion occur from repeated initializations and teardowns since
qcom_scm_pas_metadata_release() is missing from the normal iris_fw_unload()
cleanup path?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260610-glymur-v8-0-1c79b9d51fc0@oss.qualcomm.com?part=5

  reply	other threads:[~2026-06-10  6:45 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-10  6:29 [PATCH v8 00/12] media: iris: Add support for glymur platform Vishnu Reddy
2026-06-10  6:29 ` [PATCH v8 01/12] media: iris: Add iris vpu bus support Vishnu Reddy
2026-06-10  6:46   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 02/12] iommu: Add iris-vpu-bus to iommu_buses Vishnu Reddy
2026-06-10  6:29 ` [PATCH v8 03/12] dt-bindings: media: qcom,glymur-iris: Add glymur video codec Vishnu Reddy
2026-06-10  6:29 ` [PATCH v8 04/12] media: iris: Add context bank hooks for platform specific initialization Vishnu Reddy
2026-06-10  6:40   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 05/12] media: iris: Enable Secure PAS support with IOMMU managed by Linux Vishnu Reddy
2026-06-10  6:45   ` sashiko-bot [this message]
2026-06-10  6:29 ` [PATCH v8 06/12] media: iris: Replace enum-indexed clock and power domain tables with per-block structures Vishnu Reddy
2026-06-10  6:49   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 07/12] media: iris: Add power sequence for glymur Vishnu Reddy
2026-06-10  6:46   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 08/12] media: iris: Handle CPU_CS_SCIACMDARG3 register write via program bootup registers hook Vishnu Reddy
2026-06-10  6:40   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 09/12] media: iris: Add support to select core for dual core platforms Vishnu Reddy
2026-06-10  6:53   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 10/12] media: iris: Add platform data for glymur Vishnu Reddy
2026-06-10  6:54   ` sashiko-bot
2026-06-10  6:29 ` [PATCH v8 11/12] arm64: dts: qcom: glymur: Add iris video node Vishnu Reddy
2026-06-10  8:44   ` Bryan O'Donoghue
2026-06-10  6:29 ` [PATCH v8 12/12] arm64: dts: qcom: glymur-crd: Enable iris video codec node Vishnu Reddy

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