From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, matheus.bernardino@oss.qualcomm.com,
pierrick.bouvier@oss.qualcomm.com, ltaylorsimpson@gmail.com,
philmd@mailo.org, philmd@oss.qualcomm.com,
"Brian Cain" <bcain@quicinc.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v8] target/hexagon: Implement do_raise_exception()
Date: Wed, 10 Jun 2026 22:28:42 -0700 [thread overview]
Message-ID: <20260611052857.3911981-22-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260611052857.3911981-1-brian.cain@oss.qualcomm.com>
From: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/internal.h | 5 +++++
target/hexagon/op_helper.c | 14 ++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index cd06ff41d4f..33d73ed18d1 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -31,6 +31,11 @@ void hexagon_debug(CPUHexagonState *env);
extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
+void G_NORETURN do_raise_exception(CPUHexagonState *env,
+ uint32_t exception,
+ uint32_t PC,
+ uintptr_t retaddr);
+
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_hexagon_cpu;
#endif
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 359bf12f1f2..327c233c01b 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -40,6 +40,20 @@
#define SF_MANTBITS 23
/* Exceptions processing helpers */
+G_NORETURN
+void do_raise_exception(CPUHexagonState *env, uint32_t exception,
+ uint32_t PC, uintptr_t retaddr)
+{
+ CPUState *cs = env_cpu(env);
+ qemu_log_mask(CPU_LOG_INT, "%s: 0x%08" PRIx32 ", @ %08" PRIx32 "\n",
+ __func__, exception, PC);
+ ASSERT_DIRECT_TO_GUEST_UNSET(env, exception);
+
+ env->gpr[HEX_REG_PC] = PC;
+ cs->exception_index = exception;
+ cpu_loop_exit_restore(cs, retaddr);
+}
+
G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
uint32_t exception,
uintptr_t pc)
--
2.34.1
next prev parent reply other threads:[~2026-06-11 5:30 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 5:28 [PATCH v8 00/36] Hexagon system emulation - Part 1/3 Brian Cain
2026-06-11 5:28 ` [PATCH v8] docs: Add hexagon sysemu docs Brian Cain
2026-06-11 5:28 ` [PATCH v8] docs/system: Add hexagon CPU emulation Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via qemu development
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add a placeholder fp exception Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add guest, system reg number defs Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add guest, system reg number state Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add new macro definitions " Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add vmstate representation Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Define register fields for system regs Brian Cain
2026-06-11 5:28 ` Brian Cain [this message]
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add system reg insns Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add sysemu TCG overrides Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-08-14 17:33 ` Philippe Mathieu-Daudé
2026-08-18 19:51 ` Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add representation to count cycles Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add implementation of cycle counters Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add pcycle setting functionality Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-06-11 5:28 ` [PATCH v8] hw/hexagon: Declare hexagon TLB device interface Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Update TARGET_PAGE_BITS, stubs for modify_ssr/get_exe_mode Brian Cain
2026-06-17 15:03 ` Pierrick Bouvier
2026-08-12 6:59 ` Marc-André Lureau
2026-08-12 9:39 ` Philippe Mathieu-Daudé
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add hex_interrupts support Brian Cain
2026-06-17 19:34 ` Pierrick Bouvier
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