From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, matheus.bernardino@oss.qualcomm.com,
pierrick.bouvier@oss.qualcomm.com, ltaylorsimpson@gmail.com,
philmd@mailo.org, philmd@oss.qualcomm.com
Subject: [PATCH v8] hw/hexagon: Declare hexagon TLB device interface
Date: Wed, 10 Jun 2026 22:28:54 -0700 [thread overview]
Message-ID: <20260611052857.3911981-34-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260611052857.3911981-1-brian.cain@oss.qualcomm.com>
Add the hexagon TLB device interface header.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
include/hw/hexagon/hexagon_tlb.h | 46 ++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 include/hw/hexagon/hexagon_tlb.h
diff --git a/include/hw/hexagon/hexagon_tlb.h b/include/hw/hexagon/hexagon_tlb.h
new file mode 100644
index 00000000000..90d9ed84043
--- /dev/null
+++ b/include/hw/hexagon/hexagon_tlb.h
@@ -0,0 +1,46 @@
+/*
+ * Hexagon TLB QOM Device
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_HEXAGON_TLB_H
+#define HW_HEXAGON_TLB_H
+
+#include "hw/core/sysbus.h"
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+#include "exec/mmu-access-type.h"
+#include "monitor/monitor.h"
+#define TYPE_HEXAGON_TLB "hexagon-tlb"
+OBJECT_DECLARE_SIMPLE_TYPE(HexagonTLBState, HEXAGON_TLB)
+
+struct HexagonTLBState {
+ SysBusDevice parent_obj;
+
+ uint32_t num_entries;
+ uint64_t *entries;
+};
+
+uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index);
+void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t value);
+
+bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid,
+ uint32_t VA, MMUAccessType access_type,
+ hwaddr *PA, int *prot, uint64_t *size,
+ int32_t *excp, int *cause_code, int mmu_idx);
+
+uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid,
+ uint32_t VA, int *cause_code);
+
+int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry,
+ uint64_t index);
+
+void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb);
+
+bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry);
+
+uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb);
+
+#endif /* HW_HEXAGON_TLB_H */
--
2.34.1
next prev parent reply other threads:[~2026-06-11 5:33 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 5:28 [PATCH v8 00/36] Hexagon system emulation - Part 1/3 Brian Cain
2026-06-11 5:28 ` [PATCH v8] docs: Add hexagon sysemu docs Brian Cain
2026-06-11 5:28 ` [PATCH v8] docs/system: Add hexagon CPU emulation Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via qemu development
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add a placeholder fp exception Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add guest, system reg number defs Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add guest, system reg number state Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add new macro definitions " Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add vmstate representation Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Define register fields for system regs Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Implement do_raise_exception() Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add system reg insns Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add sysemu TCG overrides Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add representation to count cycles Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add implementation of cycle counters Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add pcycle setting functionality Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-06-11 5:28 ` Brian Cain [this message]
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Update TARGET_PAGE_BITS, stubs for modify_ssr/get_exe_mode Brian Cain
2026-06-17 15:03 ` Pierrick Bouvier
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-06-11 5:28 ` [PATCH v8] target/hexagon: Add hex_interrupts support Brian Cain
2026-06-17 19:34 ` Pierrick Bouvier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260611052857.3911981-34-brian.cain@oss.qualcomm.com \
--to=brian.cain@oss.qualcomm.com \
--cc=ltaylorsimpson@gmail.com \
--cc=matheus.bernardino@oss.qualcomm.com \
--cc=philmd@mailo.org \
--cc=philmd@oss.qualcomm.com \
--cc=pierrick.bouvier@oss.qualcomm.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.