From: "Michael S. Tsirkin" <mst@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Gavin Shan" <gshan@redhat.com>, "Peter Xu" <peterx@redhat.com>,
"Pavel Hrdina" <phrdina@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org, jugraham@redhat.com,
shan.gavin@gmail.com, "Alex Williamson" <alex@shazbot.org>,
"David Hildenbrand" <david@kernel.org>
Subject: Re: [PATCH RFCv1] virtio: Inherit max bounce buffer size from bus parent if possible
Date: Thu, 11 Jun 2026 12:13:14 -0400 [thread overview]
Message-ID: <20260611120325-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20260611110156-mutt-send-email-mst@kernel.org>
On Thu, Jun 11, 2026 at 11:05:35AM -0400, Michael S. Tsirkin wrote:
> > If and where we need to provide guarantees about "this access will
> > really definitely only do this size access and it won't break it
> > apart or anything like that" then we need to either be using compiler
> > atomics or else inline asm.
BTW you meant intrinsics, of course, but speaking of atomics, they do
not work on device ram, or not yet. E.g. kvm does not support them
when exiting to qemu I think (only if emulating within kernel)
and it prints "emulating exchange as write".
We are quite far from "arbitrary access" even on pure device RAM.
--
MST
next prev parent reply other threads:[~2026-06-11 16:13 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-08 0:18 [PATCH RFCv1] virtio: Inherit max bounce buffer size from bus parent if possible Gavin Shan
2026-06-08 8:55 ` Daniel P. Berrangé
2026-06-08 11:11 ` Gavin Shan
2026-06-08 11:38 ` Daniel P. Berrangé
2026-06-09 2:08 ` Gavin Shan
2026-06-09 16:25 ` Peter Xu
2026-06-10 0:32 ` Gavin Shan
2026-06-10 9:54 ` Pavel Hrdina
2026-06-10 10:55 ` Gavin Shan
2026-06-10 12:12 ` Michael S. Tsirkin
2026-06-10 12:19 ` Gavin Shan
2026-06-10 12:27 ` Michael S. Tsirkin
2026-06-10 13:00 ` Gavin Shan
2026-06-10 13:54 ` Gavin Shan
2026-06-10 14:06 ` Michael S. Tsirkin
2026-06-10 15:36 ` Peter Xu
2026-06-10 16:11 ` Peter Maydell
2026-06-10 16:19 ` Michael S. Tsirkin
2026-06-10 19:10 ` Peter Xu
2026-06-10 21:03 ` Michael S. Tsirkin
2026-06-10 21:27 ` Peter Xu
2026-06-10 21:44 ` Michael S. Tsirkin
2026-06-10 16:18 ` Michael S. Tsirkin
2026-06-11 4:33 ` Gavin Shan
2026-06-11 5:31 ` Michael S. Tsirkin
2026-06-11 6:28 ` Gavin Shan
2026-06-11 6:34 ` Michael S. Tsirkin
2026-06-11 12:33 ` Gavin Shan
2026-06-11 12:48 ` Peter Maydell
2026-06-11 14:10 ` Michael S. Tsirkin
2026-06-11 14:55 ` Peter Maydell
2026-06-11 15:05 ` Michael S. Tsirkin
2026-06-11 15:25 ` Michael S. Tsirkin
2026-06-11 15:29 ` Peter Maydell
2026-06-11 15:57 ` Michael S. Tsirkin
2026-06-11 16:16 ` Peter Maydell
2026-06-11 16:42 ` Michael S. Tsirkin
2026-06-11 16:53 ` Peter Maydell
2026-06-11 17:02 ` Michael S. Tsirkin
2026-06-11 16:13 ` Michael S. Tsirkin [this message]
2026-06-11 6:51 ` Michael S. Tsirkin
2026-06-10 12:23 ` Pavel Hrdina
2026-06-10 14:04 ` Gavin Shan
2026-06-10 14:08 ` Michael S. Tsirkin
2026-06-10 9:49 ` Michael S. Tsirkin
2026-06-10 18:30 ` Stefan Hajnoczi
2026-06-10 21:00 ` Michael S. Tsirkin
2026-06-11 14:20 ` Stefan Hajnoczi
2026-06-11 14:45 ` Michael S. Tsirkin
2026-06-11 15:04 ` Peter Maydell
2026-06-11 15:09 ` Michael S. Tsirkin
2026-06-11 1:19 ` Gavin Shan
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