Re: [PATCH v8 14/27] drm/i915/display: Make set_pipeconf use the fw variants

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Incomplete migration to _fw register access variants in VRR handling causes 'sleeping in atomic context' BUG on PREEMPT_RT.
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commit 3e8bb0c4e5f9821d1b47fa3563431c605e96b128
Author: Maarten Lankhorst <dev@lankhorst.se>

drm/i915/display: Make set_pipeconf use the fw variants

The calls are used inside the critical section when updating
the gamma mode, and thus should use the _fw variants to prevent
locks.

> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2e3ade44f28ee..03b15765843a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c

[ ... ]

> @@ -3042,8 +3042,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
>  
> -	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
> -	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
> +	intel_de_write_fw(display, TRANSCONF(display, cpu_transcoder), val);
> +	/* posting read */
> +	intel_de_read_fw(display, TRANSCONF(display, cpu_transcoder));
>  }

[Severity: High]
This is a pre-existing issue, but since the goal is to prevent sleeping
in atomic context on PREEMPT_RT during the vblank evasion section, are
there other register accesses in this path that need the fw variants?

Several VRR functions still use the sleepable non-fw register access
variants inside the atomic section where local IRQs are disabled:

1. intel_vrr_set_vrr_timings() and intel_vrr_enable_dc_balancing() use
intel_de_write() and intel_de_read() and are called from
intel_vrr_enable(), which executes via commit_pipe_post_planes().

2. intel_vrr_set_transcoder_timings() uses intel_de_write() and executes
via commit_pipe_pre_planes() -> intel_pipe_fastset().

For example, in drivers/gpu/drm/i915/display/intel_vrr.c:

intel_vrr_set_vrr_timings() {
        ...
        intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
                       intel_vrr_hw_vmin(crtc_state) - 1);
        ...
}

Could these non-fw accesses trigger the same PREEMPT_RT splat?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260615201846.307297-1-dev@lankhorst.se?part=14