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From: David Laight <david.laight.linux@gmail.com>
To: Guo Ren <guoren@kernel.org>
Cc: zhangzhanpeng.jasper@bytedance.com, alex@ghiti.fr,
	aou@eecs.berkeley.edu, cuiyunhui@bytedance.com,
	iommu@lists.linux.dev, joro@8bytes.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	luxu.kernel@bytedance.com, palmer@dabbelt.com, pjw@kernel.org,
	robin.murphy@arm.com, tjeznach@rivosinc.com, will@kernel.org,
	yuanzhu@bytedance.com
Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses
Date: Tue, 16 Jun 2026 11:36:51 +0100	[thread overview]
Message-ID: <20260616113651.1048a19a@pumpkin> (raw)
In-Reply-To: <20260615123821.373248-1-guoren@kernel.org>

On Mon, 15 Jun 2026 12:38:17 +0000
Guo Ren <guoren@kernel.org> wrote:

> Hi Zhanpeng Zhang,
..
> 3. Only performance-monitoring counters require 64-bit IO access or the
> high-low-high do-while retry strategy. For ordinary status and control
> MMIO registers, a single read is sufficient.

Actually this sequence should be enough for a counter:
	hi = read_hi();
	lo = read_lo();
	if (hi != read_hi()) {
		// Pick a value that happened while doing the reads.
		hi++;
		lo = 0;
	}

-- David

WARNING: multiple messages have this Message-ID (diff)
From: David Laight <david.laight.linux@gmail.com>
To: Guo Ren <guoren@kernel.org>
Cc: zhangzhanpeng.jasper@bytedance.com, alex@ghiti.fr,
	aou@eecs.berkeley.edu, cuiyunhui@bytedance.com,
	iommu@lists.linux.dev, joro@8bytes.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	luxu.kernel@bytedance.com, palmer@dabbelt.com, pjw@kernel.org,
	robin.murphy@arm.com, tjeznach@rivosinc.com, will@kernel.org,
	yuanzhu@bytedance.com
Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses
Date: Tue, 16 Jun 2026 11:36:51 +0100	[thread overview]
Message-ID: <20260616113651.1048a19a@pumpkin> (raw)
In-Reply-To: <20260615123821.373248-1-guoren@kernel.org>

On Mon, 15 Jun 2026 12:38:17 +0000
Guo Ren <guoren@kernel.org> wrote:

> Hi Zhanpeng Zhang,
..
> 3. Only performance-monitoring counters require 64-bit IO access or the
> high-low-high do-while retry strategy. For ordinary status and control
> MMIO registers, a single read is sufficient.

Actually this sequence should be enough for a counter:
	hi = read_hi();
	lo = read_lo();
	if (hi != read_hi()) {
		// Pick a value that happened while doing the reads.
		hi++;
		lo = 0;
	}

-- David

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2026-06-16 10:36 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-15  6:48 [PATCH v1] iommu/riscv: Support 32-bit register accesses Zhanpeng Zhang
2026-06-15  6:48 ` Zhanpeng Zhang
2026-06-15  8:21 ` Andreas Schwab
2026-06-15  8:21   ` Andreas Schwab
2026-06-15  9:51   ` [External] " Zhanpeng Zhang
2026-06-15  9:51     ` Zhanpeng Zhang
2026-06-15  9:59 ` David Laight
2026-06-15  9:59   ` David Laight
2026-06-15 13:21   ` [External] " Zhanpeng Zhang
2026-06-15 13:21     ` Zhanpeng Zhang
2026-06-15 12:38 ` Guo Ren
2026-06-15 12:38   ` Guo Ren
2026-06-15 13:23   ` [External] " Zhanpeng Zhang
2026-06-15 13:23     ` Zhanpeng Zhang
2026-06-16 10:36   ` David Laight [this message]
2026-06-16 10:36     ` David Laight
2026-06-16 15:47     ` Guo Ren
2026-06-16 15:47       ` Guo Ren
2026-06-16 19:51       ` David Laight
2026-06-16 19:51         ` David Laight

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