[PATCH v2 07/11] drm/i915/vrr: Fix the CMRR enabling/disabling sequence

[Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>]

Write TRANS_CMRR_N_HI register last in the sequence of
CMRR register writes, hardware will consider this as a
marker to double buffer the registers at next rising edge
of delayed vblank. Remove the related FIXME comments.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 83f25184c66c..0113f413f04b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -878,10 +878,10 @@ intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
 		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
 		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
 		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 }
 
 static void
@@ -892,8 +892,8 @@ intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
-	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
 	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
 }
 
 static void
@@ -994,12 +994,6 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
-	/*
-	 * FIXME this might be broken as bspec seems to imply that
-	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
-	 * when enabling CMRR (but not when disabling CMRR?).
-	 */
-
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 
 	intel_cmtg_set_vrr_ctl(crtc_state);
-- 
2.48.1