From: Saif Abrar <saif.abrar@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: harshpb@linux.ibm.com, clg@kaod.org, npiggin@gmail.com,
fbarrat@linux.ibm.com, mst@redhat.com,
marcel.apfelbaum@gmail.com, cohuck@redhat.com,
pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com,
danielhb413@gmail.com, kowal@linux.ibm.com,
chalapathi.v@linux.ibm.com, calebs@linux.ibm.com,
milesg@linux.ibm.com, jishnuvw@linux.ibm.com,
adityag@linux.ibm.com, amachhiw@linux.ibm.com
Subject: [PATCH v5 9/9] pnv/phb5: Mask off LSI Source-ID based on number of interrupts
Date: Wed, 17 Jun 2026 04:50:58 -0500 [thread overview]
Message-ID: <20260617095058.652789-10-saif.abrar@linux.ibm.com> (raw)
In-Reply-To: <20260617095058.652789-1-saif.abrar@linux.ibm.com>
From: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small PHB.
Signed-off-by: Saif Abrar <saif.abrar@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Jishnu Warrier <Jishnu.Warrier@ibm.com>
---
v3: Updates for coding guidelines.
v2: Introduced method pnv_phb4_xsrc_reset().
hw/pci-host/pnv_phb4.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 91b2064113..08c96aef7d 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -491,6 +491,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
lsi_base <<= 3;
+ lsi_base &= (xsrc->nr_irqs - 1);
/* TODO: handle reset values of PHB_LSI_SRC_ID */
if (!lsi_base) {
@@ -1943,6 +1944,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4Class *phb4c)
/* TODO: Add more RO-masks as regs are implemented in the model */
}
+static void pnv_phb4_xsrc_reset(PnvPHB4 *phb)
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
+ pnv_phb4_update_xsrc(phb);
+}
+
static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
{
STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
@@ -1999,10 +2006,11 @@ static void pnv_phb4_reset(Object *obj, ResetType type)
PnvPHB4 *phb = PNV_PHB4(obj);
pnv_phb4_pbl_core_reset(phb);
+
+ pnv_phb4_xsrc_reset(phb);
pnv_phb4_err_reg_reset(phb);
pnv_phb4_pcie_stack_reg_reset(phb);
pnv_phb4_regb_err_reg_reset(phb);
- phb->regs[PHB_PCIE_CRESET >> 3] = 0xE000000000000000;
}
static void pnv_phb4_instance_init(Object *obj)
@@ -2076,8 +2084,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
return;
}
- pnv_phb4_update_xsrc(phb);
-
phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
pnv_phb4_xscom_realize(phb);
--
2.52.0
next prev parent reply other threads:[~2026-06-17 9:52 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-17 9:50 [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec Saif Abrar
2026-06-17 9:50 ` [PATCH v5 1/9] qtest/phb5: Add testbench for PHB Saif Abrar
2026-06-23 18:24 ` Caleb Schlossin
2026-06-25 17:02 ` Aditya Gupta
2026-06-17 9:50 ` [PATCH v5 2/9] pnv/phb5: Add reset logic to PHB5 Saif Abrar
2026-06-23 18:24 ` Caleb Schlossin
2026-06-17 9:50 ` [PATCH v5 3/9] pnv/phb5: Implement sticky reset logic in PHB5 Saif Abrar
2026-06-23 18:42 ` Caleb Schlossin
2026-06-17 9:50 ` [PATCH v5 4/9] pnv/phb5: Implement read-only and write-only bits of registers Saif Abrar
2026-06-23 18:52 ` Caleb Schlossin
2026-06-17 9:50 ` [PATCH v5 5/9] pnv/phb5: Implement write-clear and return 1's on unimplemented reg read Saif Abrar
2026-06-23 18:53 ` Caleb Schlossin
2026-06-17 9:50 ` [PATCH v5 6/9] pnv/phb5: Set link-active status in HPSTAT and LMR registers Saif Abrar
2026-06-23 20:43 ` Caleb Schlossin
2026-06-17 9:50 ` [PATCH v5 7/9] pnv/phb5: Set link speed and width in the DLP training control register Saif Abrar
2026-06-23 20:43 ` Caleb Schlossin
2026-06-17 9:50 ` [PATCH v5 8/9] pnv/phb5: Implement IODA PCT table Saif Abrar
2026-06-23 20:44 ` Caleb Schlossin
2026-06-29 11:08 ` Aditya Gupta
2026-06-17 9:50 ` Saif Abrar [this message]
2026-06-23 20:44 ` [PATCH v5 9/9] pnv/phb5: Mask off LSI Source-ID based on number of interrupts Caleb Schlossin
2026-06-24 4:47 ` [PATCH v5 0/9] pnv/phb5: Update PHB4 to the latest PHB5 spec Harsh Prateek Bora
2026-06-25 8:02 ` Aditya Gupta
2026-06-30 10:22 ` Saif Abrar
2026-06-30 13:39 ` Michael S. Tsirkin
2026-06-30 14:47 ` Cédric Le Goater
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