* [PATCH 1/1 v4] drm/xe: Wait for HW clearance before issuing the next TLB inval.
2026-06-24 22:51 [PATCH 0/1 v4] drm/xe: Wait for HW clearance before issuing the next TLB inval fei.yang
@ 2026-06-24 22:51 ` fei.yang
2026-06-24 23:00 ` ✓ CI.KUnit: success for " Patchwork
2026-06-25 0:37 ` ✗ Xe.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: fei.yang @ 2026-06-24 22:51 UTC (permalink / raw)
To: intel-xe; +Cc: Fei Yang, Matthew Brost, Stuart Summers, Roper Matthew D
From: Fei Yang <fei.yang@intel.com>
Hardware requires the software to poll the valid bit and make sure
it's cleared before issuing a new TLB invalidation request.
We also need to avoid racing against GuC on TLB invalidations. In
order to achieve that, check for pending TLB invalidation in tlb_inval
list.
Signed-off-by: Fei Yang <fei.yang@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Roper Matthew D <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 70 +++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
index cf6d106e6036..815fbd059112 100644
--- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
@@ -8,6 +8,7 @@
#include "xe_device.h"
#include "xe_exec_queue.h"
#include "xe_exec_queue_types.h"
+#include "xe_gt_printk.h"
#include "xe_gt_stats.h"
#include "xe_gt_types.h"
#include "xe_guc.h"
@@ -60,6 +61,12 @@ static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval, u32 seqno)
static int send_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval, u32 seqno)
{
+ /*
+ * Timeout for MMIO-based TLB invalidation polling. Make it 250ms
+ * based on hw_tlb_timeout = HZ/4 defined in tlb_inval_timeout_delay().
+ */
+ const long hw_tlb_timeout = HZ / 4;
+
struct xe_guc *guc = tlb_inval->private;
struct xe_gt *gt = guc_to_gt(guc);
struct xe_device *xe = guc_to_xe(guc);
@@ -79,19 +86,82 @@ static int send_tlb_inval_ggtt(struct xe_tlb_inval *tlb_inval, u32 seqno)
return send_tlb_inval(guc, action, ARRAY_SIZE(action));
} else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
struct xe_mmio *mmio = >->mmio;
+ int err;
if (IS_SRIOV_VF(xe))
return -ECANCELED;
+ /*
+ * seqno_lock serializes MMIO-based TLB invalidations to prevent
+ * races between concurrent requests issued through GuC CT and
+ * direct MMIO writes.
+ */
+ lockdep_assert_held(&tlb_inval->seqno_lock);
+
+ /*
+ * If there are pending GuC TLB invalidation requests MMIO-based
+ * requests should be avoided.
+ */
+ if (!xe_tlb_inval_idle(tlb_inval)) {
+ xe_gt_dbg(gt, "MMIO TLB INV skipped due to pending GuC INv\n");
+ return -ECANCELED;
+ }
+
CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
+ /*
+ * HW requires the valid bit to be clear before writing a
+ * new request.
+ */
+ err = xe_mmio_wait32(mmio, PVC_GUC_TLB_INV_DESC0,
+ PVC_GUC_TLB_INV_DESC0_VALID, 0,
+ hw_tlb_timeout, NULL, false);
+ if (err) {
+ xe_gt_err(gt, "MMIO TLB INV pre-write poll timeout\n");
+ return -ECANCELED;
+ }
+
xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
PVC_GUC_TLB_INV_DESC1_INVALIDATE);
xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
PVC_GUC_TLB_INV_DESC0_VALID);
+
+ /*
+ * Poll for clearance of the valid bit after writing to
+ * ensure the request has been consumed and to avoid races
+ * between TLB invalidation through GuC and MMIO.
+ */
+ err = xe_mmio_wait32(mmio, PVC_GUC_TLB_INV_DESC0,
+ PVC_GUC_TLB_INV_DESC0_VALID, 0,
+ hw_tlb_timeout, NULL, false);
+ if (err)
+ xe_gt_err(gt, "MMIO TLB INV post-write poll timeout\n");
} else {
+ /*
+ * HW requires the valid bit to be clear before writing a
+ * new request.
+ */
+ err = xe_mmio_wait32(mmio, GUC_TLB_INV_CR,
+ GUC_TLB_INV_CR_INVALIDATE, 0,
+ hw_tlb_timeout, NULL, false);
+ if (err) {
+ xe_gt_err(gt, "MMIO TLB INV pre-write poll timeout\n");
+ return -ECANCELED;
+ }
+
xe_mmio_write32(mmio, GUC_TLB_INV_CR,
GUC_TLB_INV_CR_INVALIDATE);
+
+ /*
+ * Poll for clearance of the valid bit after writing to
+ * ensure the request has been consumed and to avoid races
+ * between TLB invalidation through GuC and MMIO.
+ */
+ err = xe_mmio_wait32(mmio, GUC_TLB_INV_CR,
+ GUC_TLB_INV_CR_INVALIDATE, 0,
+ hw_tlb_timeout, NULL, false);
+ if (err)
+ xe_gt_err(gt, "MMIO TLB INV post-write poll timeout\n");
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* ✓ CI.KUnit: success for drm/xe: Wait for HW clearance before issuing the next TLB inval.
2026-06-24 22:51 [PATCH 0/1 v4] drm/xe: Wait for HW clearance before issuing the next TLB inval fei.yang
2026-06-24 22:51 ` [PATCH 1/1 " fei.yang
@ 2026-06-24 23:00 ` Patchwork
2026-06-25 0:37 ` ✗ Xe.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2026-06-24 23:00 UTC (permalink / raw)
To: fei.yang; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Wait for HW clearance before issuing the next TLB inval.
URL : https://patchwork.freedesktop.org/series/169123/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:59:08] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:59:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:59:44] Starting KUnit Kernel (1/1)...
[22:59:44] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:59:44] ================== guc_buf (11 subtests) ===================
[22:59:44] [PASSED] test_smallest
[22:59:44] [PASSED] test_largest
[22:59:44] [PASSED] test_granular
[22:59:44] [PASSED] test_unique
[22:59:44] [PASSED] test_overlap
[22:59:44] [PASSED] test_reusable
[22:59:44] [PASSED] test_too_big
[22:59:44] [PASSED] test_flush
[22:59:44] [PASSED] test_lookup
[22:59:44] [PASSED] test_data
[22:59:44] [PASSED] test_class
[22:59:44] ===================== [PASSED] guc_buf =====================
[22:59:44] =================== guc_dbm (7 subtests) ===================
[22:59:44] [PASSED] test_empty
[22:59:44] [PASSED] test_default
[22:59:44] ======================== test_size ========================
[22:59:44] [PASSED] 4
[22:59:44] [PASSED] 8
[22:59:44] [PASSED] 32
[22:59:44] [PASSED] 256
[22:59:44] ==================== [PASSED] test_size ====================
[22:59:44] ======================= test_reuse ========================
[22:59:44] [PASSED] 4
[22:59:44] [PASSED] 8
[22:59:44] [PASSED] 32
[22:59:44] [PASSED] 256
[22:59:44] =================== [PASSED] test_reuse ====================
[22:59:44] =================== test_range_overlap ====================
[22:59:44] [PASSED] 4
[22:59:44] [PASSED] 8
[22:59:44] [PASSED] 32
[22:59:44] [PASSED] 256
[22:59:44] =============== [PASSED] test_range_overlap ================
[22:59:44] =================== test_range_compact ====================
[22:59:44] [PASSED] 4
[22:59:44] [PASSED] 8
[22:59:44] [PASSED] 32
[22:59:44] [PASSED] 256
[22:59:44] =============== [PASSED] test_range_compact ================
[22:59:44] ==================== test_range_spare =====================
[22:59:44] [PASSED] 4
[22:59:44] [PASSED] 8
[22:59:44] [PASSED] 32
[22:59:44] [PASSED] 256
[22:59:44] ================ [PASSED] test_range_spare =================
[22:59:44] ===================== [PASSED] guc_dbm =====================
[22:59:44] =================== guc_idm (6 subtests) ===================
[22:59:44] [PASSED] bad_init
[22:59:44] [PASSED] no_init
[22:59:44] [PASSED] init_fini
[22:59:44] [PASSED] check_used
[22:59:44] [PASSED] check_quota
[22:59:44] [PASSED] check_all
[22:59:44] ===================== [PASSED] guc_idm =====================
[22:59:44] ================== no_relay (3 subtests) ===================
[22:59:44] [PASSED] xe_drops_guc2pf_if_not_ready
[22:59:44] [PASSED] xe_drops_guc2vf_if_not_ready
[22:59:44] [PASSED] xe_rejects_send_if_not_ready
[22:59:44] ==================== [PASSED] no_relay =====================
[22:59:44] ================== pf_relay (14 subtests) ==================
[22:59:44] [PASSED] pf_rejects_guc2pf_too_short
[22:59:44] [PASSED] pf_rejects_guc2pf_too_long
[22:59:44] [PASSED] pf_rejects_guc2pf_no_payload
[22:59:44] [PASSED] pf_fails_no_payload
[22:59:44] [PASSED] pf_fails_bad_origin
[22:59:44] [PASSED] pf_fails_bad_type
[22:59:44] [PASSED] pf_txn_reports_error
[22:59:44] [PASSED] pf_txn_sends_pf2guc
[22:59:44] [PASSED] pf_sends_pf2guc
[22:59:44] [SKIPPED] pf_loopback_nop
[22:59:44] [SKIPPED] pf_loopback_echo
[22:59:45] [SKIPPED] pf_loopback_fail
[22:59:45] [SKIPPED] pf_loopback_busy
[22:59:45] [SKIPPED] pf_loopback_retry
[22:59:45] ==================== [PASSED] pf_relay =====================
[22:59:45] ================== vf_relay (3 subtests) ===================
[22:59:45] [PASSED] vf_rejects_guc2vf_too_short
[22:59:45] [PASSED] vf_rejects_guc2vf_too_long
[22:59:45] [PASSED] vf_rejects_guc2vf_no_payload
[22:59:45] ==================== [PASSED] vf_relay =====================
[22:59:45] ================ pf_gt_config (9 subtests) =================
[22:59:45] [PASSED] fair_contexts_1vf
[22:59:45] [PASSED] fair_doorbells_1vf
[22:59:45] [PASSED] fair_ggtt_1vf
[22:59:45] ====================== fair_vram_1vf ======================
[22:59:45] [PASSED] 3.50 GiB
[22:59:45] [PASSED] 11.5 GiB
[22:59:45] [PASSED] 15.5 GiB
[22:59:45] [PASSED] 31.5 GiB
[22:59:45] [PASSED] 63.5 GiB
[22:59:45] [PASSED] 1.91 GiB
[22:59:45] ================== [PASSED] fair_vram_1vf ==================
[22:59:45] ================ fair_vram_1vf_admin_only =================
[22:59:45] [PASSED] 3.50 GiB
[22:59:45] [PASSED] 11.5 GiB
[22:59:45] [PASSED] 15.5 GiB
[22:59:45] [PASSED] 31.5 GiB
[22:59:45] [PASSED] 63.5 GiB
[22:59:45] [PASSED] 1.91 GiB
[22:59:45] ============ [PASSED] fair_vram_1vf_admin_only =============
[22:59:45] ====================== fair_contexts ======================
[22:59:45] [PASSED] 1 VF
[22:59:45] [PASSED] 2 VFs
[22:59:45] [PASSED] 3 VFs
[22:59:45] [PASSED] 4 VFs
[22:59:45] [PASSED] 5 VFs
[22:59:45] [PASSED] 6 VFs
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[22:59:45] [PASSED] 8 VFs
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[22:59:45] [PASSED] 50 VFs
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[22:59:45] [PASSED] 57 VFs
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[22:59:45] [PASSED] 61 VFs
[22:59:45] [PASSED] 62 VFs
[22:59:45] [PASSED] 63 VFs
[22:59:45] ================== [PASSED] fair_contexts ==================
[22:59:45] ===================== fair_doorbells ======================
[22:59:45] [PASSED] 1 VF
[22:59:45] [PASSED] 2 VFs
[22:59:45] [PASSED] 3 VFs
[22:59:45] [PASSED] 4 VFs
[22:59:45] [PASSED] 5 VFs
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[22:59:45] [PASSED] 40 VFs
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[22:59:45] [PASSED] 44 VFs
[22:59:45] [PASSED] 45 VFs
[22:59:45] [PASSED] 46 VFs
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[22:59:45] [PASSED] 48 VFs
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[22:59:45] [PASSED] 50 VFs
[22:59:45] [PASSED] 51 VFs
[22:59:45] [PASSED] 52 VFs
[22:59:45] [PASSED] 53 VFs
[22:59:45] [PASSED] 54 VFs
[22:59:45] [PASSED] 55 VFs
[22:59:45] [PASSED] 56 VFs
[22:59:45] [PASSED] 57 VFs
[22:59:45] [PASSED] 58 VFs
[22:59:45] [PASSED] 59 VFs
[22:59:45] [PASSED] 60 VFs
[22:59:45] [PASSED] 61 VFs
[22:59:45] [PASSED] 62 VFs
[22:59:45] [PASSED] 63 VFs
[22:59:45] ================= [PASSED] fair_doorbells ==================
[22:59:45] ======================== fair_ggtt ========================
[22:59:45] [PASSED] 1 VF
[22:59:45] [PASSED] 2 VFs
[22:59:45] [PASSED] 3 VFs
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[22:59:45] [PASSED] 61 VFs
[22:59:45] [PASSED] 62 VFs
[22:59:45] [PASSED] 63 VFs
[22:59:45] ==================== [PASSED] fair_ggtt ====================
[22:59:45] ======================== fair_vram ========================
[22:59:45] [PASSED] 1 VF
[22:59:45] [PASSED] 2 VFs
[22:59:45] [PASSED] 3 VFs
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[22:59:45] [PASSED] 29 VFs
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[22:59:45] [PASSED] 37 VFs
[22:59:45] [PASSED] 38 VFs
[22:59:45] [PASSED] 39 VFs
[22:59:45] [PASSED] 40 VFs
[22:59:45] [PASSED] 41 VFs
[22:59:45] [PASSED] 42 VFs
[22:59:45] [PASSED] 43 VFs
[22:59:45] [PASSED] 44 VFs
[22:59:45] [PASSED] 45 VFs
[22:59:45] [PASSED] 46 VFs
[22:59:45] [PASSED] 47 VFs
[22:59:45] [PASSED] 48 VFs
[22:59:45] [PASSED] 49 VFs
[22:59:45] [PASSED] 50 VFs
[22:59:45] [PASSED] 51 VFs
[22:59:45] [PASSED] 52 VFs
[22:59:45] [PASSED] 53 VFs
[22:59:45] [PASSED] 54 VFs
[22:59:45] [PASSED] 55 VFs
[22:59:45] [PASSED] 56 VFs
[22:59:45] [PASSED] 57 VFs
[22:59:45] [PASSED] 58 VFs
[22:59:45] [PASSED] 59 VFs
[22:59:45] [PASSED] 60 VFs
[22:59:45] [PASSED] 61 VFs
[22:59:45] [PASSED] 62 VFs
[22:59:45] [PASSED] 63 VFs
[22:59:45] ==================== [PASSED] fair_vram ====================
[22:59:45] ================== [PASSED] pf_gt_config ===================
[22:59:45] ===================== lmtt (1 subtest) =====================
[22:59:45] ======================== test_ops =========================
[22:59:45] [PASSED] 2-level
[22:59:45] [PASSED] multi-level
[22:59:45] ==================== [PASSED] test_ops =====================
[22:59:45] ====================== [PASSED] lmtt =======================
[22:59:45] ================= pf_service (11 subtests) =================
[22:59:45] [PASSED] pf_negotiate_any
[22:59:45] [PASSED] pf_negotiate_base_match
[22:59:45] [PASSED] pf_negotiate_base_newer
[22:59:45] [PASSED] pf_negotiate_base_next
[22:59:45] [SKIPPED] pf_negotiate_base_older
[22:59:45] [PASSED] pf_negotiate_base_prev
[22:59:45] [PASSED] pf_negotiate_latest_match
[22:59:45] [PASSED] pf_negotiate_latest_newer
[22:59:45] [PASSED] pf_negotiate_latest_next
[22:59:45] [SKIPPED] pf_negotiate_latest_older
[22:59:45] [SKIPPED] pf_negotiate_latest_prev
[22:59:45] =================== [PASSED] pf_service ====================
[22:59:45] ================= xe_guc_g2g (2 subtests) ==================
[22:59:45] ============== xe_live_guc_g2g_kunit_default ==============
[22:59:45] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[22:59:45] ============== xe_live_guc_g2g_kunit_allmem ===============
[22:59:45] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[22:59:45] =================== [SKIPPED] xe_guc_g2g ===================
[22:59:45] =================== xe_mocs (2 subtests) ===================
[22:59:45] ================ xe_live_mocs_kernel_kunit ================
[22:59:45] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:59:45] ================ xe_live_mocs_reset_kunit =================
[22:59:45] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:59:45] ==================== [SKIPPED] xe_mocs =====================
[22:59:45] ================= xe_migrate (2 subtests) ==================
[22:59:45] ================= xe_migrate_sanity_kunit =================
[22:59:45] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:59:45] ================== xe_validate_ccs_kunit ==================
[22:59:45] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:59:45] =================== [SKIPPED] xe_migrate ===================
[22:59:45] ================== xe_dma_buf (1 subtest) ==================
[22:59:45] ==================== xe_dma_buf_kunit =====================
[22:59:45] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:59:45] =================== [SKIPPED] xe_dma_buf ===================
[22:59:45] ================= xe_bo_shrink (1 subtest) =================
[22:59:45] =================== xe_bo_shrink_kunit ====================
[22:59:45] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:59:45] ================== [SKIPPED] xe_bo_shrink ==================
[22:59:45] ==================== xe_bo (2 subtests) ====================
[22:59:45] ================== xe_ccs_migrate_kunit ===================
[22:59:45] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:59:45] ==================== xe_bo_evict_kunit ====================
[22:59:45] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:59:45] ===================== [SKIPPED] xe_bo ======================
[22:59:45] ==================== args (13 subtests) ====================
[22:59:45] [PASSED] count_args_test
[22:59:45] [PASSED] call_args_example
[22:59:45] [PASSED] call_args_test
[22:59:45] [PASSED] drop_first_arg_example
[22:59:45] [PASSED] drop_first_arg_test
[22:59:45] [PASSED] first_arg_example
[22:59:45] [PASSED] first_arg_test
[22:59:45] [PASSED] last_arg_example
[22:59:45] [PASSED] last_arg_test
[22:59:45] [PASSED] pick_arg_example
[22:59:45] [PASSED] if_args_example
[22:59:45] [PASSED] if_args_test
[22:59:45] [PASSED] sep_comma_example
[22:59:45] ====================== [PASSED] args =======================
[22:59:45] =================== xe_pci (3 subtests) ====================
[22:59:45] ==================== check_graphics_ip ====================
[22:59:45] [PASSED] 12.00 Xe_LP
[22:59:45] [PASSED] 12.10 Xe_LP+
[22:59:45] [PASSED] 12.55 Xe_HPG
[22:59:45] [PASSED] 12.60 Xe_HPC
[22:59:45] [PASSED] 12.70 Xe_LPG
[22:59:45] [PASSED] 12.71 Xe_LPG
[22:59:45] [PASSED] 12.74 Xe_LPG+
[22:59:45] [PASSED] 20.01 Xe2_HPG
[22:59:45] [PASSED] 20.02 Xe2_HPG
[22:59:45] [PASSED] 20.04 Xe2_LPG
[22:59:45] [PASSED] 30.00 Xe3_LPG
[22:59:45] [PASSED] 30.01 Xe3_LPG
[22:59:45] [PASSED] 30.03 Xe3_LPG
[22:59:45] [PASSED] 30.04 Xe3_LPG
[22:59:45] [PASSED] 30.05 Xe3_LPG
[22:59:45] [PASSED] 35.10 Xe3p_LPG
[22:59:45] [PASSED] 35.11 Xe3p_XPC
[22:59:45] ================ [PASSED] check_graphics_ip ================
[22:59:45] ===================== check_media_ip ======================
[22:59:45] [PASSED] 12.00 Xe_M
[22:59:45] [PASSED] 12.55 Xe_HPM
[22:59:45] [PASSED] 13.00 Xe_LPM+
[22:59:45] [PASSED] 13.01 Xe2_HPM
[22:59:45] [PASSED] 20.00 Xe2_LPM
[22:59:45] [PASSED] 30.00 Xe3_LPM
[22:59:45] [PASSED] 30.02 Xe3_LPM
[22:59:45] [PASSED] 35.00 Xe3p_LPM
[22:59:45] [PASSED] 35.03 Xe3p_HPM
[22:59:45] ================= [PASSED] check_media_ip ==================
[22:59:45] =================== check_platform_desc ===================
[22:59:45] [PASSED] 0x9A60 (TIGERLAKE)
[22:59:45] [PASSED] 0x9A68 (TIGERLAKE)
[22:59:45] [PASSED] 0x9A70 (TIGERLAKE)
[22:59:45] [PASSED] 0x9A40 (TIGERLAKE)
[22:59:45] [PASSED] 0x9A49 (TIGERLAKE)
[22:59:45] [PASSED] 0x9A59 (TIGERLAKE)
[22:59:45] [PASSED] 0x9A78 (TIGERLAKE)
[22:59:45] [PASSED] 0x9AC0 (TIGERLAKE)
[22:59:45] [PASSED] 0x9AC9 (TIGERLAKE)
[22:59:45] [PASSED] 0x9AD9 (TIGERLAKE)
[22:59:45] [PASSED] 0x9AF8 (TIGERLAKE)
[22:59:45] [PASSED] 0x4C80 (ROCKETLAKE)
[22:59:45] [PASSED] 0x4C8A (ROCKETLAKE)
[22:59:45] [PASSED] 0x4C8B (ROCKETLAKE)
[22:59:45] [PASSED] 0x4C8C (ROCKETLAKE)
[22:59:45] [PASSED] 0x4C90 (ROCKETLAKE)
[22:59:45] [PASSED] 0x4C9A (ROCKETLAKE)
[22:59:45] [PASSED] 0x4680 (ALDERLAKE_S)
[22:59:45] [PASSED] 0x4682 (ALDERLAKE_S)
[22:59:45] [PASSED] 0x4688 (ALDERLAKE_S)
[22:59:45] [PASSED] 0x468A (ALDERLAKE_S)
[22:59:45] [PASSED] 0x468B (ALDERLAKE_S)
[22:59:45] [PASSED] 0x4690 (ALDERLAKE_S)
[22:59:45] [PASSED] 0x4692 (ALDERLAKE_S)
[22:59:45] [PASSED] 0x4693 (ALDERLAKE_S)
[22:59:45] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46AA (ALDERLAKE_P)
[22:59:45] [PASSED] 0x462A (ALDERLAKE_P)
[22:59:45] [PASSED] 0x4626 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x4628 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46B0 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:59:45] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:59:45] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:59:45] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:59:45] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:59:45] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:59:45] [PASSED] 0xA721 (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA720 (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:59:45] [PASSED] 0xA780 (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA781 (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA782 (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA783 (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA788 (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA789 (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA78A (ALDERLAKE_S)
[22:59:45] [PASSED] 0xA78B (ALDERLAKE_S)
[22:59:45] [PASSED] 0x4905 (DG1)
[22:59:45] [PASSED] 0x4906 (DG1)
[22:59:45] [PASSED] 0x4907 (DG1)
[22:59:45] [PASSED] 0x4908 (DG1)
[22:59:45] [PASSED] 0x4909 (DG1)
[22:59:45] [PASSED] 0x56C0 (DG2)
[22:59:45] [PASSED] 0x56C2 (DG2)
[22:59:45] [PASSED] 0x56C1 (DG2)
[22:59:45] [PASSED] 0x7D51 (METEORLAKE)
[22:59:45] [PASSED] 0x7DD1 (METEORLAKE)
[22:59:45] [PASSED] 0x7D41 (METEORLAKE)
[22:59:45] [PASSED] 0x7D67 (METEORLAKE)
[22:59:45] [PASSED] 0xB640 (METEORLAKE)
[22:59:45] [PASSED] 0x56A0 (DG2)
[22:59:45] [PASSED] 0x56A1 (DG2)
[22:59:45] [PASSED] 0x56A2 (DG2)
[22:59:45] [PASSED] 0x56BE (DG2)
[22:59:45] [PASSED] 0x56BF (DG2)
[22:59:45] [PASSED] 0x5690 (DG2)
[22:59:45] [PASSED] 0x5691 (DG2)
[22:59:45] [PASSED] 0x5692 (DG2)
[22:59:45] [PASSED] 0x56A5 (DG2)
[22:59:45] [PASSED] 0x56A6 (DG2)
[22:59:45] [PASSED] 0x56B0 (DG2)
[22:59:45] [PASSED] 0x56B1 (DG2)
[22:59:45] [PASSED] 0x56BA (DG2)
[22:59:45] [PASSED] 0x56BB (DG2)
[22:59:45] [PASSED] 0x56BC (DG2)
[22:59:45] [PASSED] 0x56BD (DG2)
[22:59:45] [PASSED] 0x5693 (DG2)
[22:59:45] [PASSED] 0x5694 (DG2)
[22:59:45] [PASSED] 0x5695 (DG2)
[22:59:45] [PASSED] 0x56A3 (DG2)
[22:59:45] [PASSED] 0x56A4 (DG2)
[22:59:45] [PASSED] 0x56B2 (DG2)
[22:59:45] [PASSED] 0x56B3 (DG2)
[22:59:45] [PASSED] 0x5696 (DG2)
[22:59:45] [PASSED] 0x5697 (DG2)
[22:59:45] [PASSED] 0xB69 (PVC)
[22:59:45] [PASSED] 0xB6E (PVC)
[22:59:45] [PASSED] 0xBD4 (PVC)
[22:59:45] [PASSED] 0xBD5 (PVC)
[22:59:45] [PASSED] 0xBD6 (PVC)
[22:59:45] [PASSED] 0xBD7 (PVC)
[22:59:45] [PASSED] 0xBD8 (PVC)
[22:59:45] [PASSED] 0xBD9 (PVC)
[22:59:45] [PASSED] 0xBDA (PVC)
[22:59:45] [PASSED] 0xBDB (PVC)
[22:59:45] [PASSED] 0xBE0 (PVC)
[22:59:45] [PASSED] 0xBE1 (PVC)
[22:59:45] [PASSED] 0xBE5 (PVC)
[22:59:45] [PASSED] 0x7D40 (METEORLAKE)
[22:59:45] [PASSED] 0x7D45 (METEORLAKE)
[22:59:45] [PASSED] 0x7D55 (METEORLAKE)
[22:59:45] [PASSED] 0x7D60 (METEORLAKE)
[22:59:45] [PASSED] 0x7DD5 (METEORLAKE)
[22:59:45] [PASSED] 0x6420 (LUNARLAKE)
[22:59:45] [PASSED] 0x64A0 (LUNARLAKE)
[22:59:45] [PASSED] 0x64B0 (LUNARLAKE)
[22:59:45] [PASSED] 0xE202 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE209 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE20B (BATTLEMAGE)
[22:59:45] [PASSED] 0xE20C (BATTLEMAGE)
[22:59:45] [PASSED] 0xE20D (BATTLEMAGE)
[22:59:45] [PASSED] 0xE210 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE211 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE212 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE216 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE220 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE221 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE222 (BATTLEMAGE)
[22:59:45] [PASSED] 0xE223 (BATTLEMAGE)
[22:59:45] [PASSED] 0xB080 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB081 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB082 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB083 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB084 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB085 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB086 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB087 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB08F (PANTHERLAKE)
[22:59:45] [PASSED] 0xB090 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:59:45] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:59:45] [PASSED] 0xFD80 (PANTHERLAKE)
[22:59:45] [PASSED] 0xFD81 (PANTHERLAKE)
[22:59:45] [PASSED] 0xD740 (NOVALAKE_S)
[22:59:45] [PASSED] 0xD741 (NOVALAKE_S)
[22:59:45] [PASSED] 0xD742 (NOVALAKE_S)
[22:59:45] [PASSED] 0xD743 (NOVALAKE_S)
[22:59:45] [PASSED] 0xD745 (NOVALAKE_S)
[22:59:45] [PASSED] 0xD74A (NOVALAKE_S)
[22:59:45] [PASSED] 0xD74B (NOVALAKE_S)
[22:59:45] [PASSED] 0x674C (CRESCENTISLAND)
[22:59:45] [PASSED] 0x674D (CRESCENTISLAND)
[22:59:45] [PASSED] 0x674E (CRESCENTISLAND)
[22:59:45] [PASSED] 0x674F (CRESCENTISLAND)
[22:59:45] [PASSED] 0x6750 (CRESCENTISLAND)
[22:59:45] [PASSED] 0xD750 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD751 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD752 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD753 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD754 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD755 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD756 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD757 (NOVALAKE_P)
[22:59:45] [PASSED] 0xD75F (NOVALAKE_P)
[22:59:45] =============== [PASSED] check_platform_desc ===============
[22:59:45] ===================== [PASSED] xe_pci ======================
[22:59:45] ============= xe_rtp_tables_test (4 subtests) ==============
[22:59:45] ================== xe_rtp_table_gt_test ===================
[22:59:45] [PASSED] gt_was/14011060649
[22:59:45] [PASSED] gt_was/14011059788
[22:59:45] [PASSED] gt_was/14015795083
[22:59:45] [PASSED] gt_was/16021867713
[22:59:45] [PASSED] gt_was/14019449301
[22:59:45] [PASSED] gt_was/16028005424
[22:59:45] [PASSED] gt_was/14026578760
[22:59:45] [PASSED] gt_was/1409420604
[22:59:45] [PASSED] gt_was/1408615072
[22:59:45] [PASSED] gt_was/22010523718
[22:59:45] [PASSED] gt_was/14011006942
[22:59:45] [PASSED] gt_was/14014830051
[22:59:45] [PASSED] gt_was/18018781329
[22:59:45] [PASSED] gt_was/1509235366
[22:59:45] [PASSED] gt_was/18018781329
[22:59:45] [PASSED] gt_was/16016694945
[22:59:45] [PASSED] gt_was/14018575942
[22:59:45] [PASSED] gt_was/22016670082
[22:59:45] [PASSED] gt_was/22016670082
[22:59:45] [PASSED] gt_was/14017421178
[22:59:45] [PASSED] gt_was/16025250150
[22:59:45] [PASSED] gt_was/14021871409
[22:59:45] [PASSED] gt_was/16021865536
[22:59:45] [PASSED] gt_was/14021486841
[22:59:45] [PASSED] gt_was/14025160223
[22:59:45] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[22:59:45] [PASSED] gt_was/14025635424
[22:59:45] [PASSED] gt_was/16028005424
[22:59:45] ============== [PASSED] xe_rtp_table_gt_test ===============
[22:59:45] ================== xe_rtp_table_gt_test ===================
[22:59:45] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[22:59:45] [PASSED] gt_tunings/Tuning: 32B Access Enable
[22:59:45] [PASSED] gt_tunings/Tuning: L3 cache
[22:59:45] [PASSED] gt_tunings/Tuning: L3 cache - media
[22:59:45] [PASSED] gt_tunings/Tuning: Compression Overfetch
[22:59:45] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[22:59:45] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[22:59:45] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[22:59:45] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[22:59:45] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[22:59:45] [PASSED] gt_tunings/Tuning: Stateless compression control
[22:59:45] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[22:59:45] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[22:59:45] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[22:59:45] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[22:59:45] ============== [PASSED] xe_rtp_table_gt_test ===============
[22:59:45] ================== xe_rtp_table_oob_test ==================
[22:59:45] [PASSED] oob_was/1607983814
[22:59:45] [PASSED] oob_was/16010904313
[22:59:45] [PASSED] oob_was/18022495364
[22:59:45] [PASSED] oob_was/22012773006
[22:59:45] [PASSED] oob_was/14014475959
[22:59:45] [PASSED] oob_was/22011391025
[22:59:45] [PASSED] oob_was/22012727170
[22:59:45] [PASSED] oob_was/22012727685
[22:59:45] [PASSED] oob_was/22016596838
[22:59:45] [PASSED] oob_was/18020744125
[22:59:45] [PASSED] oob_was/1409600907
[22:59:45] [PASSED] oob_was/22014953428
[22:59:45] [PASSED] oob_was/16017236439
[22:59:45] [PASSED] oob_was/14019821291
[22:59:45] [PASSED] oob_was/14015076503
[22:59:45] [PASSED] oob_was/14018913170
[22:59:45] [PASSED] oob_was/14018094691
[22:59:45] [PASSED] oob_was/18024947630
[22:59:45] [PASSED] oob_was/16022287689
[22:59:45] [PASSED] oob_was/13011645652
[22:59:45] [PASSED] oob_was/14022293748
[22:59:45] [PASSED] oob_was/22019794406
[22:59:45] [PASSED] oob_was/22019338487
[22:59:45] [PASSED] oob_was/16023588340
[22:59:45] [PASSED] oob_was/14019789679
[22:59:45] [PASSED] oob_was/14022866841
[22:59:45] [PASSED] oob_was/16021333562
[22:59:45] [PASSED] oob_was/14016712196
[22:59:45] [PASSED] oob_was/14015568240
[22:59:45] [PASSED] oob_was/18013179988
[22:59:45] [PASSED] oob_was/1508761755
[22:59:45] [PASSED] oob_was/16023105232
[22:59:45] [PASSED] oob_was/16026508708
[22:59:45] [PASSED] oob_was/14020001231
[22:59:45] [PASSED] oob_was/16023683509
[22:59:45] [PASSED] oob_was/14025515070
[22:59:45] [PASSED] oob_was/15015404425_disable
[22:59:45] [PASSED] oob_was/16026007364
[22:59:45] [PASSED] oob_was/14020316580
[22:59:45] [PASSED] oob_was/14025883347
[22:59:45] [PASSED] oob_was/16029380221
[22:59:45] ============== [PASSED] xe_rtp_table_oob_test ==============
[22:59:45] ================ xe_rtp_table_dev_oob_test ================
[22:59:45] [PASSED] device_oob_was/22010954014
[22:59:45] [PASSED] device_oob_was/15015404425
[22:59:45] [PASSED] device_oob_was/22019338487_display
[22:59:45] [PASSED] device_oob_was/14022085890
[22:59:45] [PASSED] device_oob_was/14026539277
[22:59:45] [PASSED] device_oob_was/14026633728
[22:59:45] [PASSED] device_oob_was/14026746987
[22:59:45] [PASSED] device_oob_was/14026779378
[22:59:45] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[22:59:45] =============== [PASSED] xe_rtp_tables_test ================
[22:59:45] =================== xe_rtp (3 subtests) ====================
[22:59:45] =================== xe_rtp_rules_tests ====================
[22:59:45] [PASSED] no
[22:59:45] [PASSED] yes
[22:59:45] [PASSED] no-and-no
[22:59:45] [PASSED] no-and-yes
[22:59:45] [PASSED] yes-and-no
[22:59:45] [PASSED] yes-and-yes
[22:59:45] [PASSED] no-or-no
[22:59:45] [PASSED] no-or-yes
[22:59:45] [PASSED] yes-or-no
[22:59:45] [PASSED] yes-or-yes
[22:59:45] [PASSED] no-yes-or-yes-no
[22:59:45] [PASSED] no-yes-or-yes-yes
[22:59:45] [PASSED] yes-yes-or-no-yes
[22:59:45] [PASSED] yes-yes-or-yes-yes
[22:59:45] [PASSED] no-no-or-yes-or-no
[22:59:45] [PASSED] or
[22:59:45] [PASSED] or-yes
[22:59:45] [PASSED] or-no
[22:59:45] [PASSED] yes-or
[22:59:45] [PASSED] no-or
[22:59:45] [PASSED] no-or-or-yes
[22:59:45] [PASSED] yes-or-or-no
[22:59:45] [PASSED] no-or-or-no
[22:59:45] [PASSED] missing-context-engine-class
[22:59:45] [PASSED] missing-context-engine-class-or-yes
[22:59:45] [PASSED] missing-context-engine-class-or-or-yes
[22:59:45] =============== [PASSED] xe_rtp_rules_tests ================
[22:59:45] =============== xe_rtp_process_to_sr_tests ================
[22:59:45] [PASSED] coalesce-same-reg
[22:59:45] [PASSED] coalesce-same-reg-literal-and-func
[22:59:45] [PASSED] no-match-no-add
[22:59:45] [PASSED] two-regs-two-entries
[22:59:45] [PASSED] clr-one-set-other
[22:59:45] [PASSED] set-field
[22:59:45] [PASSED] conflict-duplicate
[22:59:45] [PASSED] conflict-not-disjoint
[22:59:45] [PASSED] conflict-not-disjoint-literal-and-func
[22:59:45] [PASSED] conflict-reg-type
[22:59:45] [PASSED] bad-mcr-reg-forced-to-regular
[22:59:45] [PASSED] bad-regular-reg-forced-to-mcr
[22:59:45] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:59:45] ================== xe_rtp_process_tests ===================
[22:59:45] [PASSED] active1
[22:59:45] [PASSED] active2
[22:59:45] [PASSED] active-inactive
[22:59:45] [PASSED] inactive-active
[22:59:45] [PASSED] inactive-active-inactive
[22:59:45] [PASSED] inactive-inactive-inactive
[22:59:45] ============== [PASSED] xe_rtp_process_tests ===============
[22:59:45] ===================== [PASSED] xe_rtp ======================
[22:59:45] ==================== xe_wa (1 subtest) =====================
[22:59:45] ======================== xe_wa_gt =========================
[22:59:45] [PASSED] TIGERLAKE B0
[22:59:45] [PASSED] DG1 A0
[22:59:45] [PASSED] DG1 B0
[22:59:45] [PASSED] ALDERLAKE_S A0
[22:59:45] [PASSED] ALDERLAKE_S B0
[22:59:45] [PASSED] ALDERLAKE_S C0
[22:59:45] [PASSED] ALDERLAKE_S D0
[22:59:45] [PASSED] ALDERLAKE_P A0
[22:59:45] [PASSED] ALDERLAKE_P B0
[22:59:45] [PASSED] ALDERLAKE_P C0
[22:59:45] [PASSED] ALDERLAKE_S RPLS D0
[22:59:45] [PASSED] ALDERLAKE_P RPLU E0
[22:59:45] [PASSED] DG2 G10 C0
[22:59:45] [PASSED] DG2 G11 B1
[22:59:45] [PASSED] DG2 G12 A1
[22:59:45] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:59:45] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:59:45] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[22:59:45] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[22:59:45] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[22:59:45] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[22:59:45] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[22:59:45] ==================== [PASSED] xe_wa_gt =====================
[22:59:45] ====================== [PASSED] xe_wa ======================
[22:59:45] ============================================================
[22:59:45] Testing complete. Ran 719 tests: passed: 701, skipped: 18
[22:59:45] Elapsed time: 36.421s total, 4.291s configuring, 31.464s building, 0.638s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:59:45] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:59:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:00:11] Starting KUnit Kernel (1/1)...
[23:00:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:00:11] ============ drm_test_pick_cmdline (2 subtests) ============
[23:00:11] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:00:11] =============== drm_test_pick_cmdline_named ===============
[23:00:11] [PASSED] NTSC
[23:00:11] [PASSED] NTSC-J
[23:00:11] [PASSED] PAL
[23:00:11] [PASSED] PAL-M
[23:00:11] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:00:11] ============== [PASSED] drm_test_pick_cmdline ==============
[23:00:11] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:00:11] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:00:11] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:00:11] =========== drm_validate_clone_mode (2 subtests) ===========
[23:00:11] ============== drm_test_check_in_clone_mode ===============
[23:00:11] [PASSED] in_clone_mode
[23:00:11] [PASSED] not_in_clone_mode
[23:00:11] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:00:11] =============== drm_test_check_valid_clones ===============
[23:00:11] [PASSED] not_in_clone_mode
[23:00:11] [PASSED] valid_clone
[23:00:11] [PASSED] invalid_clone
[23:00:11] =========== [PASSED] drm_test_check_valid_clones ===========
[23:00:11] ============= [PASSED] drm_validate_clone_mode =============
[23:00:11] ============= drm_validate_modeset (1 subtest) =============
[23:00:11] [PASSED] drm_test_check_connector_changed_modeset
[23:00:11] ============== [PASSED] drm_validate_modeset ===============
[23:00:11] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:00:11] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:00:11] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:00:11] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:00:11] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[23:00:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:00:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:00:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:00:11] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[23:00:11] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:00:11] ============== drm_bridge_alloc (2 subtests) ===============
[23:00:11] [PASSED] drm_test_drm_bridge_alloc_basic
[23:00:11] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:00:11] ================ [PASSED] drm_bridge_alloc =================
[23:00:11] ============= drm_bridge_bus_fmt (5 subtests) ==============
[23:00:11] [PASSED] drm_test_bridge_rgb_yuv_rgb
[23:00:11] [PASSED] drm_test_bridge_must_convert_to_yuv444
[23:00:11] [PASSED] drm_test_bridge_hdmi_auto_rgb
[23:00:11] [PASSED] drm_test_bridge_auto_first
[23:00:11] [PASSED] drm_test_bridge_rgb_yuv_no_path
[23:00:11] =============== [PASSED] drm_bridge_bus_fmt ================
[23:00:11] ============= drm_cmdline_parser (40 subtests) =============
[23:00:11] [PASSED] drm_test_cmdline_force_d_only
[23:00:11] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:00:11] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:00:11] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:00:11] [PASSED] drm_test_cmdline_force_e_only
[23:00:11] [PASSED] drm_test_cmdline_res
[23:00:11] [PASSED] drm_test_cmdline_res_vesa
[23:00:11] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:00:11] [PASSED] drm_test_cmdline_res_rblank
[23:00:11] [PASSED] drm_test_cmdline_res_bpp
[23:00:11] [PASSED] drm_test_cmdline_res_refresh
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:00:11] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:00:11] [PASSED] drm_test_cmdline_res_margins_force_on
[23:00:11] [PASSED] drm_test_cmdline_res_vesa_margins
[23:00:11] [PASSED] drm_test_cmdline_name
[23:00:11] [PASSED] drm_test_cmdline_name_bpp
[23:00:11] [PASSED] drm_test_cmdline_name_option
[23:00:11] [PASSED] drm_test_cmdline_name_bpp_option
[23:00:11] [PASSED] drm_test_cmdline_rotate_0
[23:00:11] [PASSED] drm_test_cmdline_rotate_90
[23:00:11] [PASSED] drm_test_cmdline_rotate_180
[23:00:11] [PASSED] drm_test_cmdline_rotate_270
[23:00:11] [PASSED] drm_test_cmdline_hmirror
[23:00:11] [PASSED] drm_test_cmdline_vmirror
[23:00:11] [PASSED] drm_test_cmdline_margin_options
[23:00:11] [PASSED] drm_test_cmdline_multiple_options
[23:00:11] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:00:11] [PASSED] drm_test_cmdline_extra_and_option
[23:00:11] [PASSED] drm_test_cmdline_freestanding_options
[23:00:11] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:00:11] [PASSED] drm_test_cmdline_panel_orientation
[23:00:11] ================ drm_test_cmdline_invalid =================
[23:00:11] [PASSED] margin_only
[23:00:11] [PASSED] interlace_only
[23:00:11] [PASSED] res_missing_x
[23:00:11] [PASSED] res_missing_y
[23:00:11] [PASSED] res_bad_y
[23:00:11] [PASSED] res_missing_y_bpp
[23:00:11] [PASSED] res_bad_bpp
[23:00:11] [PASSED] res_bad_refresh
[23:00:11] [PASSED] res_bpp_refresh_force_on_off
[23:00:11] [PASSED] res_invalid_mode
[23:00:11] [PASSED] res_bpp_wrong_place_mode
[23:00:11] [PASSED] name_bpp_refresh
[23:00:11] [PASSED] name_refresh
[23:00:11] [PASSED] name_refresh_wrong_mode
[23:00:11] [PASSED] name_refresh_invalid_mode
[23:00:11] [PASSED] rotate_multiple
[23:00:11] [PASSED] rotate_invalid_val
[23:00:11] [PASSED] rotate_truncated
[23:00:11] [PASSED] invalid_option
[23:00:11] [PASSED] invalid_tv_option
[23:00:11] [PASSED] truncated_tv_option
[23:00:11] ============ [PASSED] drm_test_cmdline_invalid =============
[23:00:11] =============== drm_test_cmdline_tv_options ===============
[23:00:11] [PASSED] NTSC
[23:00:11] [PASSED] NTSC_443
[23:00:11] [PASSED] NTSC_J
[23:00:11] [PASSED] PAL
[23:00:11] [PASSED] PAL_M
[23:00:11] [PASSED] PAL_N
[23:00:11] [PASSED] SECAM
[23:00:11] [PASSED] MONO_525
[23:00:11] [PASSED] MONO_625
[23:00:11] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:00:11] =============== [PASSED] drm_cmdline_parser ================
[23:00:11] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:00:11] [PASSED] drm_test_connector_hdmi_init_valid
[23:00:11] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:00:11] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:00:11] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:00:11] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:00:11] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:00:11] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:00:11] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:00:11] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:00:11] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:00:11] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:00:11] [PASSED] supported_formats=0x5 yuv420_allowed=1
[23:00:11] [PASSED] supported_formats=0x5 yuv420_allowed=0
[23:00:11] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:00:11] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:00:11] [PASSED] drm_test_connector_hdmi_init_null_product
[23:00:11] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:00:11] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:00:11] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:00:11] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:00:11] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:00:11] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:00:11] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:00:11] ========= drm_test_connector_hdmi_init_type_valid =========
[23:00:11] [PASSED] HDMI-A
[23:00:11] [PASSED] HDMI-B
[23:00:11] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:00:11] ======== drm_test_connector_hdmi_init_type_invalid ========
[23:00:11] [PASSED] Unknown
[23:00:11] [PASSED] VGA
[23:00:11] [PASSED] DVI-I
[23:00:11] [PASSED] DVI-D
[23:00:11] [PASSED] DVI-A
[23:00:11] [PASSED] Composite
[23:00:11] [PASSED] SVIDEO
[23:00:11] [PASSED] LVDS
[23:00:11] [PASSED] Component
[23:00:11] [PASSED] DIN
[23:00:11] [PASSED] DP
[23:00:11] [PASSED] TV
[23:00:11] [PASSED] eDP
[23:00:11] [PASSED] Virtual
[23:00:11] [PASSED] DSI
[23:00:11] [PASSED] DPI
[23:00:11] [PASSED] Writeback
[23:00:11] [PASSED] SPI
[23:00:11] [PASSED] USB
[23:00:11] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:00:11] ============ [PASSED] drmm_connector_hdmi_init =============
[23:00:11] ============= drmm_connector_init (3 subtests) =============
[23:00:11] [PASSED] drm_test_drmm_connector_init
[23:00:11] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:00:11] ========= drm_test_drmm_connector_init_type_valid =========
[23:00:11] [PASSED] Unknown
[23:00:11] [PASSED] VGA
[23:00:11] [PASSED] DVI-I
[23:00:11] [PASSED] DVI-D
[23:00:11] [PASSED] DVI-A
[23:00:11] [PASSED] Composite
[23:00:11] [PASSED] SVIDEO
[23:00:11] [PASSED] LVDS
[23:00:11] [PASSED] Component
[23:00:11] [PASSED] DIN
[23:00:11] [PASSED] DP
[23:00:11] [PASSED] HDMI-A
[23:00:11] [PASSED] HDMI-B
[23:00:11] [PASSED] TV
[23:00:11] [PASSED] eDP
[23:00:11] [PASSED] Virtual
[23:00:11] [PASSED] DSI
[23:00:11] [PASSED] DPI
[23:00:11] [PASSED] Writeback
[23:00:11] [PASSED] SPI
[23:00:11] [PASSED] USB
[23:00:11] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:00:11] =============== [PASSED] drmm_connector_init ===============
[23:00:11] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_init
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:00:11] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[23:00:11] [PASSED] Unknown
[23:00:11] [PASSED] VGA
[23:00:11] [PASSED] DVI-I
[23:00:11] [PASSED] DVI-D
[23:00:11] [PASSED] DVI-A
[23:00:11] [PASSED] Composite
[23:00:11] [PASSED] SVIDEO
[23:00:11] [PASSED] LVDS
[23:00:11] [PASSED] Component
[23:00:11] [PASSED] DIN
[23:00:11] [PASSED] DP
[23:00:11] [PASSED] HDMI-A
[23:00:11] [PASSED] HDMI-B
[23:00:11] [PASSED] TV
[23:00:11] [PASSED] eDP
[23:00:11] [PASSED] Virtual
[23:00:11] [PASSED] DSI
[23:00:11] [PASSED] DPI
[23:00:11] [PASSED] Writeback
[23:00:11] [PASSED] SPI
[23:00:11] [PASSED] USB
[23:00:11] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:00:11] ======== drm_test_drm_connector_dynamic_init_name =========
[23:00:11] [PASSED] Unknown
[23:00:11] [PASSED] VGA
[23:00:11] [PASSED] DVI-I
[23:00:11] [PASSED] DVI-D
[23:00:11] [PASSED] DVI-A
[23:00:11] [PASSED] Composite
[23:00:11] [PASSED] SVIDEO
[23:00:11] [PASSED] LVDS
[23:00:11] [PASSED] Component
[23:00:11] [PASSED] DIN
[23:00:11] [PASSED] DP
[23:00:11] [PASSED] HDMI-A
[23:00:11] [PASSED] HDMI-B
[23:00:11] [PASSED] TV
[23:00:11] [PASSED] eDP
[23:00:11] [PASSED] Virtual
[23:00:11] [PASSED] DSI
[23:00:11] [PASSED] DPI
[23:00:11] [PASSED] Writeback
[23:00:11] [PASSED] SPI
[23:00:11] [PASSED] USB
[23:00:11] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:00:11] =========== [PASSED] drm_connector_dynamic_init ============
[23:00:11] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:00:11] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:00:11] ======= drm_connector_dynamic_register (7 subtests) ========
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:00:11] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:00:11] ========= [PASSED] drm_connector_dynamic_register ==========
[23:00:11] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:00:11] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:00:11] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:00:11] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:00:11] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:00:11] ========== drm_test_get_tv_mode_from_name_valid ===========
[23:00:11] [PASSED] NTSC
[23:00:11] [PASSED] NTSC-443
[23:00:11] [PASSED] NTSC-J
[23:00:11] [PASSED] PAL
[23:00:11] [PASSED] PAL-M
[23:00:11] [PASSED] PAL-N
[23:00:11] [PASSED] SECAM
[23:00:11] [PASSED] Mono
[23:00:11] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:00:11] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:00:11] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:00:11] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:00:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:00:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:00:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:00:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:00:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:00:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:00:11] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[23:00:11] [PASSED] VIC 96
[23:00:11] [PASSED] VIC 97
[23:00:11] [PASSED] VIC 101
[23:00:11] [PASSED] VIC 102
[23:00:11] [PASSED] VIC 106
[23:00:11] [PASSED] VIC 107
[23:00:11] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:00:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:00:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:00:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:00:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:00:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:00:11] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:00:11] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:00:11] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[23:00:11] [PASSED] Automatic
[23:00:11] [PASSED] Full
[23:00:11] [PASSED] Limited 16:235
[23:00:11] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:00:11] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:00:11] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:00:11] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:00:11] === drm_test_drm_hdmi_connector_get_output_format_name ====
[23:00:11] [PASSED] RGB
[23:00:11] [PASSED] YUV 4:2:0
[23:00:11] [PASSED] YUV 4:2:2
[23:00:11] [PASSED] YUV 4:4:4
[23:00:11] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:00:11] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:00:11] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:00:11] ============= drm_damage_helper (21 subtests) ==============
[23:00:11] [PASSED] drm_test_damage_iter_no_damage
[23:00:11] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:00:11] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:00:11] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:00:11] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:00:11] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:00:11] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:00:11] [PASSED] drm_test_damage_iter_simple_damage
[23:00:11] [PASSED] drm_test_damage_iter_single_damage
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:00:11] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:00:11] [PASSED] drm_test_damage_iter_damage
[23:00:11] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:00:11] [PASSED] drm_test_damage_iter_damage_one_outside
[23:00:11] [PASSED] drm_test_damage_iter_damage_src_moved
[23:00:11] [PASSED] drm_test_damage_iter_damage_not_visible
[23:00:11] ================ [PASSED] drm_damage_helper ================
[23:00:11] ============== drm_dp_mst_helper (3 subtests) ==============
[23:00:11] ============== drm_test_dp_mst_calc_pbn_mode ==============
[23:00:11] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:00:11] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:00:11] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:00:11] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:00:11] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:00:11] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:00:11] ============== drm_test_dp_mst_calc_pbn_div ===============
[23:00:11] [PASSED] Link rate 2000000 lane count 4
[23:00:11] [PASSED] Link rate 2000000 lane count 2
[23:00:11] [PASSED] Link rate 2000000 lane count 1
[23:00:11] [PASSED] Link rate 1350000 lane count 4
[23:00:11] [PASSED] Link rate 1350000 lane count 2
[23:00:11] [PASSED] Link rate 1350000 lane count 1
[23:00:11] [PASSED] Link rate 1000000 lane count 4
[23:00:11] [PASSED] Link rate 1000000 lane count 2
[23:00:11] [PASSED] Link rate 1000000 lane count 1
[23:00:11] [PASSED] Link rate 810000 lane count 4
[23:00:11] [PASSED] Link rate 810000 lane count 2
[23:00:11] [PASSED] Link rate 810000 lane count 1
[23:00:11] [PASSED] Link rate 540000 lane count 4
[23:00:11] [PASSED] Link rate 540000 lane count 2
[23:00:11] [PASSED] Link rate 540000 lane count 1
[23:00:11] [PASSED] Link rate 270000 lane count 4
[23:00:11] [PASSED] Link rate 270000 lane count 2
[23:00:11] [PASSED] Link rate 270000 lane count 1
[23:00:11] [PASSED] Link rate 162000 lane count 4
[23:00:11] [PASSED] Link rate 162000 lane count 2
[23:00:11] [PASSED] Link rate 162000 lane count 1
[23:00:11] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:00:11] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[23:00:11] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:00:11] [PASSED] DP_POWER_UP_PHY with port number
[23:00:11] [PASSED] DP_POWER_DOWN_PHY with port number
[23:00:11] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:00:11] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:00:11] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:00:11] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:00:11] [PASSED] DP_QUERY_PAYLOAD with port number
[23:00:11] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:00:11] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:00:11] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:00:11] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:00:11] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:00:11] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:00:11] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:00:11] [PASSED] DP_REMOTE_I2C_READ with port number
[23:00:11] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:00:11] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:00:11] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:00:11] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:00:11] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:00:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:00:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:00:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:00:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:00:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:00:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:00:11] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:00:11] ================ [PASSED] drm_dp_mst_helper ================
[23:00:11] ================== drm_exec (7 subtests) ===================
[23:00:11] [PASSED] sanitycheck
[23:00:11] [PASSED] test_lock
[23:00:11] [PASSED] test_lock_unlock
[23:00:11] [PASSED] test_duplicates
[23:00:11] [PASSED] test_prepare
[23:00:11] [PASSED] test_prepare_array
[23:00:11] [PASSED] test_multiple_loops
[23:00:11] ==================== [PASSED] drm_exec =====================
[23:00:11] =========== drm_format_helper_test (17 subtests) ===========
[23:00:11] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:00:11] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:00:11] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:00:11] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:00:11] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:00:11] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:00:11] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:00:11] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:00:11] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:00:11] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:00:11] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:00:11] ============== drm_test_fb_xrgb8888_to_mono ===============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:00:11] ==================== drm_test_fb_swab =====================
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ================ [PASSED] drm_test_fb_swab =================
[23:00:11] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:00:11] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[23:00:11] [PASSED] single_pixel_source_buffer
[23:00:11] [PASSED] single_pixel_clip_rectangle
[23:00:11] [PASSED] well_known_colors
[23:00:11] [PASSED] destination_pitch
[23:00:11] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:00:11] ================= drm_test_fb_clip_offset =================
[23:00:11] [PASSED] pass through
[23:00:11] [PASSED] horizontal offset
[23:00:11] [PASSED] vertical offset
[23:00:11] [PASSED] horizontal and vertical offset
[23:00:11] [PASSED] horizontal offset (custom pitch)
[23:00:11] [PASSED] vertical offset (custom pitch)
[23:00:11] [PASSED] horizontal and vertical offset (custom pitch)
[23:00:11] ============= [PASSED] drm_test_fb_clip_offset =============
[23:00:11] =================== drm_test_fb_memcpy ====================
[23:00:11] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:00:11] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:00:11] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:00:11] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:00:11] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:00:11] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:00:11] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:00:11] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:00:11] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:00:11] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:00:11] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:00:11] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:00:11] =============== [PASSED] drm_test_fb_memcpy ================
[23:00:11] ============= [PASSED] drm_format_helper_test ==============
[23:00:11] ================= drm_format (18 subtests) =================
[23:00:11] [PASSED] drm_test_format_block_width_invalid
[23:00:11] [PASSED] drm_test_format_block_width_one_plane
[23:00:11] [PASSED] drm_test_format_block_width_two_plane
[23:00:11] [PASSED] drm_test_format_block_width_three_plane
[23:00:11] [PASSED] drm_test_format_block_width_tiled
[23:00:11] [PASSED] drm_test_format_block_height_invalid
[23:00:11] [PASSED] drm_test_format_block_height_one_plane
[23:00:11] [PASSED] drm_test_format_block_height_two_plane
[23:00:11] [PASSED] drm_test_format_block_height_three_plane
[23:00:11] [PASSED] drm_test_format_block_height_tiled
[23:00:11] [PASSED] drm_test_format_min_pitch_invalid
[23:00:11] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:00:11] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:00:11] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:00:11] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:00:11] [PASSED] drm_test_format_min_pitch_two_plane
[23:00:11] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:00:11] [PASSED] drm_test_format_min_pitch_tiled
[23:00:11] =================== [PASSED] drm_format ====================
[23:00:11] ============== drm_framebuffer (10 subtests) ===============
[23:00:11] ========== drm_test_framebuffer_check_src_coords ==========
[23:00:11] [PASSED] Success: source fits into fb
[23:00:11] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:00:11] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:00:11] [PASSED] Fail: overflowing fb with source width
[23:00:11] [PASSED] Fail: overflowing fb with source height
[23:00:11] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:00:11] [PASSED] drm_test_framebuffer_cleanup
[23:00:11] =============== drm_test_framebuffer_create ===============
[23:00:11] [PASSED] ABGR8888 normal sizes
[23:00:11] [PASSED] ABGR8888 max sizes
[23:00:11] [PASSED] ABGR8888 pitch greater than min required
[23:00:11] [PASSED] ABGR8888 pitch less than min required
[23:00:11] [PASSED] ABGR8888 Invalid width
[23:00:11] [PASSED] ABGR8888 Invalid buffer handle
[23:00:11] [PASSED] No pixel format
[23:00:11] [PASSED] ABGR8888 Width 0
[23:00:11] [PASSED] ABGR8888 Height 0
[23:00:11] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:00:11] [PASSED] ABGR8888 Large buffer offset
[23:00:11] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:00:11] [PASSED] ABGR8888 Invalid flag
[23:00:11] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:00:11] [PASSED] ABGR8888 Valid buffer modifier
[23:00:11] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:00:11] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] NV12 Normal sizes
[23:00:11] [PASSED] NV12 Max sizes
[23:00:11] [PASSED] NV12 Invalid pitch
[23:00:11] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:00:11] [PASSED] NV12 different modifier per-plane
[23:00:11] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:00:11] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] NV12 Modifier for inexistent plane
[23:00:11] [PASSED] NV12 Handle for inexistent plane
[23:00:11] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:00:11] [PASSED] YVU420 Normal sizes
[23:00:11] [PASSED] YVU420 Max sizes
[23:00:11] [PASSED] YVU420 Invalid pitch
[23:00:11] [PASSED] YVU420 Different pitches
[23:00:11] [PASSED] YVU420 Different buffer offsets/pitches
[23:00:11] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:00:11] [PASSED] YVU420 Valid modifier
[23:00:11] [PASSED] YVU420 Different modifiers per plane
[23:00:11] [PASSED] YVU420 Modifier for inexistent plane
[23:00:11] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:00:11] [PASSED] X0L2 Normal sizes
[23:00:11] [PASSED] X0L2 Max sizes
[23:00:11] [PASSED] X0L2 Invalid pitch
[23:00:11] [PASSED] X0L2 Pitch greater than minimum required
[23:00:11] [PASSED] X0L2 Handle for inexistent plane
[23:00:11] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:00:11] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:00:11] [PASSED] X0L2 Valid modifier
[23:00:11] [PASSED] X0L2 Modifier for inexistent plane
[23:00:11] =========== [PASSED] drm_test_framebuffer_create ===========
[23:00:11] [PASSED] drm_test_framebuffer_free
[23:00:11] [PASSED] drm_test_framebuffer_init
[23:00:11] [PASSED] drm_test_framebuffer_init_bad_format
[23:00:11] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:00:11] [PASSED] drm_test_framebuffer_lookup
[23:00:11] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:00:11] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:00:11] ================= [PASSED] drm_framebuffer =================
[23:00:11] ================ drm_gem_shmem (8 subtests) ================
[23:00:11] [PASSED] drm_gem_shmem_test_obj_create
[23:00:11] [PASSED] drm_gem_shmem_test_obj_create_private
[23:00:11] [PASSED] drm_gem_shmem_test_pin_pages
[23:00:11] [PASSED] drm_gem_shmem_test_vmap
[23:00:11] [PASSED] drm_gem_shmem_test_get_sg_table
[23:00:11] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:00:11] [PASSED] drm_gem_shmem_test_madvise
[23:00:11] [PASSED] drm_gem_shmem_test_purge
[23:00:11] ================== [PASSED] drm_gem_shmem ==================
[23:00:11] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:00:11] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[23:00:11] [PASSED] Automatic
[23:00:11] [PASSED] Full
[23:00:11] [PASSED] Limited 16:235
[23:00:11] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:00:11] [PASSED] drm_test_check_disable_connector
[23:00:11] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:00:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:00:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:00:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:00:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:00:11] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:00:11] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:00:11] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:00:11] [PASSED] drm_test_check_output_bpc_dvi
[23:00:11] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:00:11] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:00:11] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:00:11] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:00:11] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:00:11] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:00:11] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:00:11] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:00:11] ============ drm_test_check_hdmi_color_format =============
[23:00:11] [PASSED] AUTO -> RGB
[23:00:11] [PASSED] YCBCR422 -> YUV422
[23:00:11] [PASSED] YCBCR420 -> YUV420
[23:00:11] [PASSED] YCBCR444 -> YUV444
[23:00:11] [PASSED] RGB -> RGB
[23:00:11] ======== [PASSED] drm_test_check_hdmi_color_format =========
[23:00:11] ======== drm_test_check_hdmi_color_format_420_only ========
[23:00:11] [PASSED] RGB should fail
[23:00:11] [PASSED] YUV444 should fail
[23:00:11] [PASSED] YUV422 should fail
[23:00:11] [PASSED] YUV420 should work
[23:00:11] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[23:00:11] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:00:11] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:00:11] [PASSED] drm_test_check_broadcast_rgb_value
[23:00:11] [PASSED] drm_test_check_bpc_8_value
[23:00:11] [PASSED] drm_test_check_bpc_10_value
[23:00:11] [PASSED] drm_test_check_bpc_12_value
[23:00:11] [PASSED] drm_test_check_format_value
[23:00:11] [PASSED] drm_test_check_tmds_char_value
[23:00:11] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:00:11] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[23:00:11] [PASSED] drm_test_check_mode_valid
[23:00:11] [PASSED] drm_test_check_mode_valid_reject
[23:00:11] [PASSED] drm_test_check_mode_valid_reject_rate
[23:00:11] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:00:11] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[23:00:11] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[23:00:11] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[23:00:11] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:00:11] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:00:11] [PASSED] drm_test_check_infoframes
[23:00:11] [PASSED] drm_test_check_reject_avi_infoframe
[23:00:11] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:00:11] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:00:11] [PASSED] drm_test_check_reject_audio_infoframe
[23:00:11] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:00:11] ================= drm_managed (2 subtests) =================
[23:00:11] [PASSED] drm_test_managed_release_action
[23:00:11] [PASSED] drm_test_managed_run_action
[23:00:11] =================== [PASSED] drm_managed ===================
[23:00:11] =================== drm_mm (6 subtests) ====================
[23:00:11] [PASSED] drm_test_mm_init
[23:00:11] [PASSED] drm_test_mm_debug
[23:00:11] [PASSED] drm_test_mm_align32
[23:00:11] [PASSED] drm_test_mm_align64
[23:00:11] [PASSED] drm_test_mm_lowest
[23:00:11] [PASSED] drm_test_mm_highest
[23:00:11] ===================== [PASSED] drm_mm ======================
[23:00:11] ============= drm_modes_analog_tv (5 subtests) =============
[23:00:11] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:00:11] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:00:11] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:00:11] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:00:11] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:00:11] =============== [PASSED] drm_modes_analog_tv ===============
[23:00:11] ============== drm_plane_helper (2 subtests) ===============
[23:00:11] =============== drm_test_check_plane_state ================
[23:00:11] [PASSED] clipping_simple
[23:00:11] [PASSED] clipping_rotate_reflect
[23:00:11] [PASSED] positioning_simple
[23:00:11] [PASSED] upscaling
[23:00:11] [PASSED] downscaling
[23:00:11] [PASSED] rounding1
[23:00:11] [PASSED] rounding2
[23:00:11] [PASSED] rounding3
[23:00:11] [PASSED] rounding4
[23:00:11] =========== [PASSED] drm_test_check_plane_state ============
[23:00:11] =========== drm_test_check_invalid_plane_state ============
[23:00:11] [PASSED] positioning_invalid
[23:00:11] [PASSED] upscaling_invalid
[23:00:11] [PASSED] downscaling_invalid
[23:00:11] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:00:11] ================ [PASSED] drm_plane_helper =================
[23:00:11] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:00:11] ====== drm_test_connector_helper_tv_get_modes_check =======
[23:00:11] [PASSED] None
[23:00:11] [PASSED] PAL
[23:00:11] [PASSED] NTSC
[23:00:11] [PASSED] Both, NTSC Default
[23:00:11] [PASSED] Both, PAL Default
[23:00:11] [PASSED] Both, NTSC Default, with PAL on command-line
[23:00:11] [PASSED] Both, PAL Default, with NTSC on command-line
[23:00:11] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:00:11] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:00:11] ================== drm_rect (9 subtests) ===================
[23:00:11] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:00:11] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:00:11] [PASSED] drm_test_rect_clip_scaled_clipped
[23:00:11] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:00:11] ================= drm_test_rect_intersect =================
[23:00:11] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:00:11] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:00:11] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:00:11] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:00:11] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:00:11] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:00:11] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:00:11] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:00:11] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:00:11] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:00:11] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:00:11] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:00:11] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:00:11] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:00:11] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:00:11] ============= [PASSED] drm_test_rect_intersect =============
[23:00:11] ================ drm_test_rect_calc_hscale ================
[23:00:11] [PASSED] normal use
[23:00:11] [PASSED] out of max range
[23:00:11] [PASSED] out of min range
[23:00:11] [PASSED] zero dst
[23:00:11] [PASSED] negative src
[23:00:11] [PASSED] negative dst
[23:00:11] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:00:11] ================ drm_test_rect_calc_vscale ================
[23:00:11] [PASSED] normal use
[23:00:11] [PASSED] out of max range
[23:00:11] [PASSED] out of min range
[23:00:11] [PASSED] zero dst
[23:00:11] [PASSED] negative src
[23:00:11] [PASSED] negative dst
[23:00:11] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:00:11] ================== drm_test_rect_rotate ===================
[23:00:11] [PASSED] reflect-x
[23:00:11] [PASSED] reflect-y
[23:00:11] [PASSED] rotate-0
[23:00:11] [PASSED] rotate-90
[23:00:11] [PASSED] rotate-180
[23:00:11] [PASSED] rotate-270
[23:00:11] ============== [PASSED] drm_test_rect_rotate ===============
[23:00:11] ================ drm_test_rect_rotate_inv =================
[23:00:11] [PASSED] reflect-x
[23:00:11] [PASSED] reflect-y
[23:00:11] [PASSED] rotate-0
[23:00:11] [PASSED] rotate-90
[23:00:11] [PASSED] rotate-180
[23:00:11] [PASSED] rotate-270
[23:00:11] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:00:11] ==================== [PASSED] drm_rect =====================
[23:00:11] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:00:11] ============ drm_test_sysfb_build_fourcc_list =============
[23:00:11] [PASSED] no native formats
[23:00:11] [PASSED] XRGB8888 as native format
[23:00:11] [PASSED] remove duplicates
[23:00:11] [PASSED] convert alpha formats
[23:00:11] [PASSED] random formats
[23:00:11] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:00:11] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:00:11] ================== drm_fixp (2 subtests) ===================
[23:00:11] [PASSED] drm_test_int2fixp
[23:00:11] [PASSED] drm_test_sm2fixp
[23:00:11] ==================== [PASSED] drm_fixp =====================
[23:00:11] ============================================================
[23:00:11] Testing complete. Ran 639 tests: passed: 639
[23:00:11] Elapsed time: 26.244s total, 1.747s configuring, 24.281s building, 0.195s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:00:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:00:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:00:23] Starting KUnit Kernel (1/1)...
[23:00:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:00:23] ================= ttm_device (5 subtests) ==================
[23:00:23] [PASSED] ttm_device_init_basic
[23:00:23] [PASSED] ttm_device_init_multiple
[23:00:23] [PASSED] ttm_device_fini_basic
[23:00:23] [PASSED] ttm_device_init_no_vma_man
[23:00:23] ================== ttm_device_init_pools ==================
[23:00:23] [PASSED] No DMA allocations, no DMA32 required
[23:00:23] [PASSED] DMA allocations, DMA32 required
[23:00:23] [PASSED] No DMA allocations, DMA32 required
[23:00:23] [PASSED] DMA allocations, no DMA32 required
[23:00:23] ============== [PASSED] ttm_device_init_pools ==============
[23:00:23] =================== [PASSED] ttm_device ====================
[23:00:23] ================== ttm_pool (8 subtests) ===================
[23:00:23] ================== ttm_pool_alloc_basic ===================
[23:00:23] [PASSED] One page
[23:00:23] [PASSED] More than one page
[23:00:23] [PASSED] Above the allocation limit
[23:00:23] [PASSED] One page, with coherent DMA mappings enabled
[23:00:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:00:23] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:00:23] ============== ttm_pool_alloc_basic_dma_addr ==============
[23:00:23] [PASSED] One page
[23:00:23] [PASSED] More than one page
[23:00:23] [PASSED] Above the allocation limit
[23:00:23] [PASSED] One page, with coherent DMA mappings enabled
[23:00:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:00:23] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:00:23] [PASSED] ttm_pool_alloc_order_caching_match
[23:00:23] [PASSED] ttm_pool_alloc_caching_mismatch
[23:00:23] [PASSED] ttm_pool_alloc_order_mismatch
[23:00:23] [PASSED] ttm_pool_free_dma_alloc
[23:00:23] [PASSED] ttm_pool_free_no_dma_alloc
[23:00:23] [PASSED] ttm_pool_fini_basic
[23:00:23] ==================== [PASSED] ttm_pool =====================
[23:00:23] ================ ttm_resource (8 subtests) =================
[23:00:23] ================= ttm_resource_init_basic =================
[23:00:23] [PASSED] Init resource in TTM_PL_SYSTEM
[23:00:23] [PASSED] Init resource in TTM_PL_VRAM
[23:00:23] [PASSED] Init resource in a private placement
[23:00:23] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:00:23] ============= [PASSED] ttm_resource_init_basic =============
[23:00:23] [PASSED] ttm_resource_init_pinned
[23:00:23] [PASSED] ttm_resource_fini_basic
[23:00:23] [PASSED] ttm_resource_manager_init_basic
[23:00:23] [PASSED] ttm_resource_manager_usage_basic
[23:00:23] [PASSED] ttm_resource_manager_set_used_basic
[23:00:23] [PASSED] ttm_sys_man_alloc_basic
[23:00:23] [PASSED] ttm_sys_man_free_basic
[23:00:23] ================== [PASSED] ttm_resource ===================
[23:00:23] =================== ttm_tt (15 subtests) ===================
[23:00:23] ==================== ttm_tt_init_basic ====================
[23:00:23] [PASSED] Page-aligned size
[23:00:23] [PASSED] Extra pages requested
[23:00:23] ================ [PASSED] ttm_tt_init_basic ================
[23:00:23] [PASSED] ttm_tt_init_misaligned
[23:00:23] [PASSED] ttm_tt_fini_basic
[23:00:23] [PASSED] ttm_tt_fini_sg
[23:00:23] [PASSED] ttm_tt_fini_shmem
[23:00:23] [PASSED] ttm_tt_create_basic
[23:00:23] [PASSED] ttm_tt_create_invalid_bo_type
[23:00:23] [PASSED] ttm_tt_create_ttm_exists
[23:00:23] [PASSED] ttm_tt_create_failed
[23:00:23] [PASSED] ttm_tt_destroy_basic
[23:00:23] [PASSED] ttm_tt_populate_null_ttm
[23:00:23] [PASSED] ttm_tt_populate_populated_ttm
[23:00:23] [PASSED] ttm_tt_unpopulate_basic
[23:00:23] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:00:23] [PASSED] ttm_tt_swapin_basic
[23:00:23] ===================== [PASSED] ttm_tt ======================
[23:00:23] =================== ttm_bo (14 subtests) ===================
[23:00:23] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[23:00:23] [PASSED] Cannot be interrupted and sleeps
[23:00:23] [PASSED] Cannot be interrupted, locks straight away
[23:00:23] [PASSED] Can be interrupted, sleeps
[23:00:23] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:00:23] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:00:23] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:00:23] [PASSED] ttm_bo_reserve_double_resv
[23:00:23] [PASSED] ttm_bo_reserve_interrupted
[23:00:23] [PASSED] ttm_bo_reserve_deadlock
[23:00:23] [PASSED] ttm_bo_unreserve_basic
[23:00:23] [PASSED] ttm_bo_unreserve_pinned
[23:00:23] [PASSED] ttm_bo_unreserve_bulk
[23:00:23] [PASSED] ttm_bo_fini_basic
[23:00:23] [PASSED] ttm_bo_fini_shared_resv
[23:00:23] [PASSED] ttm_bo_pin_basic
[23:00:23] [PASSED] ttm_bo_pin_unpin_resource
[23:00:23] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:00:23] ===================== [PASSED] ttm_bo ======================
[23:00:23] ============== ttm_bo_validate (22 subtests) ===============
[23:00:23] ============== ttm_bo_init_reserved_sys_man ===============
[23:00:23] [PASSED] Buffer object for userspace
[23:00:23] [PASSED] Kernel buffer object
[23:00:23] [PASSED] Shared buffer object
[23:00:23] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:00:23] ============== ttm_bo_init_reserved_mock_man ==============
[23:00:23] [PASSED] Buffer object for userspace
[23:00:23] [PASSED] Kernel buffer object
[23:00:23] [PASSED] Shared buffer object
[23:00:23] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:00:23] [PASSED] ttm_bo_init_reserved_resv
[23:00:23] ================== ttm_bo_validate_basic ==================
[23:00:23] [PASSED] Buffer object for userspace
[23:00:23] [PASSED] Kernel buffer object
[23:00:23] [PASSED] Shared buffer object
[23:00:23] ============== [PASSED] ttm_bo_validate_basic ==============
[23:00:23] [PASSED] ttm_bo_validate_invalid_placement
[23:00:23] ============= ttm_bo_validate_same_placement ==============
[23:00:23] [PASSED] System manager
[23:00:23] [PASSED] VRAM manager
[23:00:23] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:00:23] [PASSED] ttm_bo_validate_failed_alloc
[23:00:23] [PASSED] ttm_bo_validate_pinned
[23:00:23] [PASSED] ttm_bo_validate_busy_placement
[23:00:23] ================ ttm_bo_validate_multihop =================
[23:00:23] [PASSED] Buffer object for userspace
[23:00:23] [PASSED] Kernel buffer object
[23:00:23] [PASSED] Shared buffer object
[23:00:23] ============ [PASSED] ttm_bo_validate_multihop =============
[23:00:23] ========== ttm_bo_validate_no_placement_signaled ==========
[23:00:23] [PASSED] Buffer object in system domain, no page vector
[23:00:23] [PASSED] Buffer object in system domain with an existing page vector
[23:00:23] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:00:23] ======== ttm_bo_validate_no_placement_not_signaled ========
[23:00:23] [PASSED] Buffer object for userspace
[23:00:23] [PASSED] Kernel buffer object
[23:00:23] [PASSED] Shared buffer object
[23:00:23] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:00:23] [PASSED] ttm_bo_validate_move_fence_signaled
[23:00:23] ========= ttm_bo_validate_move_fence_not_signaled =========
[23:00:23] [PASSED] Waits for GPU
[23:00:23] [PASSED] Tries to lock straight away
[23:00:23] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:00:23] [PASSED] ttm_bo_validate_swapout
[23:00:23] [PASSED] ttm_bo_validate_happy_evict
[23:00:23] [PASSED] ttm_bo_validate_all_pinned_evict
[23:00:23] [PASSED] ttm_bo_validate_allowed_only_evict
[23:00:23] [PASSED] ttm_bo_validate_deleted_evict
[23:00:23] [PASSED] ttm_bo_validate_busy_domain_evict
[23:00:23] [PASSED] ttm_bo_validate_evict_gutting
[23:00:23] [PASSED] ttm_bo_validate_recrusive_evict
[23:00:23] ================= [PASSED] ttm_bo_validate =================
[23:00:23] ============================================================
[23:00:23] Testing complete. Ran 102 tests: passed: 102
[23:00:23] Elapsed time: 11.583s total, 1.720s configuring, 9.648s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
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