Re: [PATCH 3/8] arm64: tegra: Enable XUSB host function on Jetson AGX Thor - sashiko-bot

From: sashiko-bot@kernel.org
To: "Wayne Chang" <waynec@nvidia.com>
Cc: vkoul@kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com,
	linux-phy@lists.infradead.org, conor+dt@kernel.org,
	robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 3/8] arm64: tegra: Enable XUSB host function on Jetson AGX Thor
Date: Mon, 29 Jun 2026 09:44:23 +0000	[thread overview]
Message-ID: <20260629094423.F1AAC1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260629093406.1118594-4-waynec@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The device tree nodes use `GIC_SPI 4096` and `GIC_SPI 4101` which incorrectly parse as hardware IRQs 4128 and 4133 due to the SPI offset of 32.
--

commit 0e16479e341627ad9fb569ac2ccd54f1ef421b1f
Author: Wayne Chang <waynec@nvidia.com>

arm64: tegra: Enable XUSB host function on Jetson AGX Thor

This commit enables XUSB host and pad controller on Jetson AGX Thor.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 2d8e7e37830ff..3433587dc5725 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -4049,6 +4049,160 @@ pci@8480000 {
>  			nvidia,bpmp = <&bpmp 5>;
>  			status = "disabled";
>  		};
> +
> +		xusb_padctl: padctl@8680000 {
> +			compatible = "nvidia,tegra264-xusb-padctl";
> +			reg = <0x00 0x8680000 0x00 0x20000>,
> +			      <0x00 0x86a0000 0x00 0x10000>;
> +			reg-names = "padctl", "ao";
> +			interrupts = <GIC_SPI 4101 IRQ_TYPE_LEVEL_HIGH>;

[Severity: High]
Does this map to the correct hardware IRQ? Using the GIC_SPI macro for an
ESPI INTID adds an offset of 32, mapping to hwirq 4133 instead of 4101.
The kernel will emit boot warnings about the SPI being out of range.

Should this be replaced with <GIC_ESPI 5 IRQ_TYPE_LEVEL_HIGH>?

[ ... ]

> +		usb@aa10000 {
> +			compatible = "nvidia,tegra264-xusb";
> +			reg = <0x00 0xaa10000 0x00 0x40000>,
> +			      <0x00 0xaa00000 0x00 0x10000>,
> +			      <0x00 0xaa50000 0x00 0x10000>;
> +			reg-names = "hcd", "fpci", "bar2";
> +
> +			interrupts-extended = <&gic GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
> +						  <&gic GIC_SPI 4096 IRQ_TYPE_LEVEL_HIGH>,

[Severity: High]
Similar to the regression above, does this sequence map correctly? Using the
GIC_SPI macro adds an offset of 32, which maps to hwirq 4128 instead of 4096.

Should this be replaced with <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629093406.1118594-1-waynec@nvidia.com?part=3

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