[PATCH v3 0/3] rockchip: odroid-m1s/rk3566 watchdog support

[PATCH v3 0/3] rockchip: odroid-m1s/rk3566 watchdog support

[Andreas Zdziarstek]

This series makes the Synopsys DesignWare watchdog usable on rk3566/rk3568
and enables it on the Hardkernel ODROID-M1S.

On current next the dw-wdt driver already probes (d62801d09441), but a
timeout or "wdt expire" still hangs the SoC: CRU_GLB_RST_CON routes the
watchdog to the second global reset by default, which causes a hung SoC.

Patch 1 routes the watchdog to the first global reset instead, same as
the PX30 implementation. Patch 2 does the same for the TSADC, so a
thermal shutdown also resets the whole SoC. Patch 3 enables the watchdog
(wdt command only, no autostart to be non-breaking) on the ODROID-M1S.

Verified on the ODROID-M1S (RK3566): a watchdog timeout cleanly reboots
the board.

Changes in v3:
- patch 1: keep the glb_rst_con write inside CONFIG_XPL_BUILD (review
  comment by Jonas)
- patch 2: fold the WDT and TSADC bits into a single glb_rst_con
  read-modify-write instead of two separate ones (review comment by Jonas)

Changes in v2:
- patch 1: access CRU_GLB_RST_CON through the rk3568_cru struct, matching
  PX30's arch_cpu_init() (review comment by Quentin)
- patch 2 (new): also route the TSADC to a first global reset (review
  comment by Quentin)
- patch 3 (was 2/2): unchanged

On the TSADC (patch 2): while checking how the ODROID-M1S comes up, I
noticed the rkbin DDR init (probably, at least I don't know what else
could set it at that stage) already sets the TSADC bit in CRU_GLB_RST_CON
before U-Boot runs. So, on this board the patch is effectively a no-op. It
still seems right to configure it explicitly in U-Boot rather than depend
on the firmware blob, and it matches what PX30 does.

Andreas Zdziarstek (3):
  rockchip: rk3568: make the WDT trigger a first global reset
  rockchip: rk3568: make the TSADC trigger a first global reset
  rockchip: odroid-m1s: enable watchdog support

 arch/arm/mach-rockchip/rk3568/rk3568.c | 11 +++++++++++
 configs/odroid-m1s-rk3566_defconfig    |  5 +++++
 2 files changed, 16 insertions(+)


base-commit: 835a18f80f25731dc818bf9b771bfa111ea3dbeb
-- 
2.53.0

[PATCH v3 1/3] rockchip: rk3568: make the WDT trigger a first global reset

[Andreas Zdziarstek]

Default is a second global reset which causes a system hang on a timeout
in U-Boot.

Access the register through the rk3568_cru struct to match how PX30 does
it in arch_cpu_init().

Verified on the Hardkernel ODROID-M1S (RK3566): a watchdog timeout now
cleanly reboots the board.

Signed-off-by: Andreas Zdziarstek <andreas.zdziarstek@gmail.com>
---
 arch/arm/mach-rockchip/rk3568/rk3568.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 2b1eafee37c..8bed529a5c1 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -9,6 +9,7 @@
 #include <misc.h>
 #include <asm/armv8/mmu.h>
 #include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/cru_rk3568.h>
 #include <asm/arch-rockchip/grf_rk3568.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3568-cru.h>
@@ -37,6 +38,9 @@
 #define CPU_GRF_BASE		0xfdc30000
 #define GRF_CORE_PVTPLL_CON0	(0x10)
 
+#define CRU_BASE		0xfdd20000
+#define WDT_GLB_SRST_CTRL	BIT(1)
+
 /* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
 	GPIO0D1_SHIFT		= 4,
@@ -117,6 +121,8 @@ void board_debug_uart_init(void)
 int arch_cpu_init(void)
 {
 #ifdef CONFIG_XPL_BUILD
+	static struct rk3568_cru * const cru = (void *)CRU_BASE;
+
 	/*
 	 * When perform idle operation, corresponding clock can
 	 * be opened or gated automatically.
@@ -145,6 +151,9 @@ int arch_cpu_init(void)
 	/* Enable VO power domain for display */
 	writel((PMU_PD_VO_DWN_ENA << 16),
 	       PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
+
+	/* Make WDT trigger a first global reset */
+	setbits_le32(&cru->glb_rst_con, WDT_GLB_SRST_CTRL);
 #endif
 	return 0;
 }
-- 
2.53.0

[PATCH v3 2/3] rockchip: rk3568: make the TSADC trigger a first global reset

[Andreas Zdziarstek]

Same rationale as the watchdog: the default second global reset leaves
the SoC hung. Set the TSADC to the first global reset as well, so a
thermal shutdown reliably resets the whole SoC.

Signed-off-by: Andreas Zdziarstek <andreas.zdziarstek@gmail.com>
---
 arch/arm/mach-rockchip/rk3568/rk3568.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 8bed529a5c1..5e6f79450db 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -40,6 +40,7 @@
 
 #define CRU_BASE		0xfdd20000
 #define WDT_GLB_SRST_CTRL	BIT(1)
+#define TSADC_GLB_SRST_CTRL	BIT(0)
 
 /* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
@@ -152,8 +153,9 @@ int arch_cpu_init(void)
 	writel((PMU_PD_VO_DWN_ENA << 16),
 	       PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
 
-	/* Make WDT trigger a first global reset */
-	setbits_le32(&cru->glb_rst_con, WDT_GLB_SRST_CTRL);
+	/* Make WDT and TSADC trigger a first global reset */
+	setbits_le32(&cru->glb_rst_con,
+		     WDT_GLB_SRST_CTRL | TSADC_GLB_SRST_CTRL);
 #endif
 	return 0;
 }
-- 
2.53.0

[PATCH v3 3/3] rockchip: odroid-m1s: enable watchdog support

[Andreas Zdziarstek]

The rk3566 ODROID-M1S has a DesignWare watchdog. Enable CONFIG_WDT,
CONFIG_DESIGNWARE_WATCHDOG and CONFIG_CMD_WDT so it can be driven via
the wdt command.

CONFIG_WATCHDOG and CONFIG_WATCHDOG_AUTOSTART are left explicitly unset
to not cause any breaking changes on existing systems.

Signed-off-by: Andreas Zdziarstek <andreas.zdziarstek@gmail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 configs/odroid-m1s-rk3566_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig
index d59882a2a59..943c0509e9e 100644
--- a/configs/odroid-m1s-rk3566_defconfig
+++ b/configs/odroid-m1s-rk3566_defconfig
@@ -30,6 +30,7 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_ROCKUSB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_WDT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_INI=y
 CONFIG_CMD_PMIC=y
@@ -87,5 +88,9 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
 CONFIG_FS_CRAMFS=y
 CONFIG_ERRNO_STR=y
-- 
2.53.0