Re: [PATCH v5 07/17] riscv: Add B to hwcap and hwprobe

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The new B base extension is added to the host's hwcap and hwprobe, but KVM support was omitted, preventing VMMs from enabling it for guests.
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commit 1f4cf004cf603a91f99c0c6776c5ca74728ca05e
Author: Andrew Jones <andrew.jones@oss.qualcomm.com>

riscv: Add B to hwcap and hwprobe

Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
are all set. Also expose B via hwprobe so that userspace can probe B directly.

> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 0acb7a01ecc0f..58523b3a1998a 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -11,6 +11,7 @@
>  #include <uapi/asm/hwcap.h>
>  
>  #define RISCV_ISA_EXT_A		('a' - 'a')
> +#define RISCV_ISA_EXT_B		('b' - 'a')

[Severity: Medium]
Since the B extension is now exposed to the host, does this patch also need
to add KVM support so VMMs can pass the B extension to guests?

Without adding KVM_RISCV_ISA_EXT_B to enum KVM_RISCV_ISA_EXT_ID in
arch/riscv/include/uapi/asm/kvm.h and the corresponding KVM_ISA_EXT_ARR(B)
mapping in arch/riscv/kvm/isa.c, KVM's ONE_REG handler will drop the
configuration request.

When a VMM configures a guest's ISA by writing to KVM_REG_RISCV_CONFIG_REG(isa)
with the B bit set, kvm_riscv_base2isa_ext() will return KVM_RISCV_ISA_EXT_MAX
and explicitly clear the bit from the requested register value.

>  #define RISCV_ISA_EXT_C		('c' - 'a')
>  #define RISCV_ISA_EXT_D		('d' - 'a')
>  #define RISCV_ISA_EXT_F		('f' - 'a')

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Sashiko AI review · https://sashiko.dev/#/patchset/20260701-rva23u64-hwprobe-v2-v5-0-2c61f94a695a@gmail.com?part=7