From: fangyu.yu@linux.alibaba.com
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Quan Zhou <zhouquan@iscas.ac.cn>,
Anup Patel <anup@brainfault.org>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, guoren@kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH] perf kvm/riscv: Fix event key collision between interrupts and exceptions
Date: Sat, 4 Jul 2026 10:36:08 +0800 [thread overview]
Message-ID: <20260704023608.24971-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
RISC-V scause encodes interrupts and exceptions in the same
cause field, with bit 63 on RV64 and bit 31 on RV32 used to
distinguish interrupts from exceptions. The lower cause bits
overlap between the two namespaces, so masking off the interrupt
bit makes distinct IRQ and exception events map to the same key.
This affects perf kvm stat exit-reason decoding. For example,
IRQ_S_TIMER and EXC_LOAD_ACCESS both use cause code 5, and can be
misreported as the wrong exit reason.
Fix this by using the full scause value as the lookup key in
event_get_key(). Also split TRAP() into TRAP_EXC() and
TRAP_IRQ() so interrupt entries are encoded with the
architecture-specific IRQ bit set, matching the value reported by
hardware.
Fixes: ceea279f9376 ("perf kvm stat: Remove use of the arch directory")
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
.../perf/util/kvm-stat-arch/kvm-stat-riscv.c | 4 +--
.../util/kvm-stat-arch/riscv_trap_types.h | 27 ++++++++++---------
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c b/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c
index 967bba261a47..829096a41a3b 100644
--- a/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c
+++ b/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c
@@ -23,10 +23,8 @@ static const char * const __kvm_events_tp[] = {
static void event_get_key(struct perf_sample *sample,
struct event_key *key)
{
- int xlen = 64; // TODO: 32-bit support.
-
key->info = 0;
- key->key = perf_sample__intval(sample, kvm_exit_reason(EM_RISCV)) & ~CAUSE_IRQ_FLAG(xlen);
+ key->key = perf_sample__intval(sample, kvm_exit_reason(EM_RISCV));
key->exit_reasons = riscv_exit_reasons;
}
diff --git a/tools/perf/util/kvm-stat-arch/riscv_trap_types.h b/tools/perf/util/kvm-stat-arch/riscv_trap_types.h
index aa5d24fab4ee..da1f1ce55326 100644
--- a/tools/perf/util/kvm-stat-arch/riscv_trap_types.h
+++ b/tools/perf/util/kvm-stat-arch/riscv_trap_types.h
@@ -38,20 +38,21 @@
#define EXC_VIRTUAL_INST_FAULT 22
#define EXC_STORE_GUEST_PAGE_FAULT 23
-#define TRAP(x) { x, #x }
+#define TRAP_EXC(x) { x, #x }
+#define TRAP_IRQ(x) { (x) | CAUSE_IRQ_FLAG(__riscv_xlen), #x }
#define kvm_riscv_trap_class \
- TRAP(IRQ_S_SOFT), TRAP(IRQ_VS_SOFT), TRAP(IRQ_M_SOFT), \
- TRAP(IRQ_S_TIMER), TRAP(IRQ_VS_TIMER), TRAP(IRQ_M_TIMER), \
- TRAP(IRQ_S_EXT), TRAP(IRQ_VS_EXT), TRAP(IRQ_M_EXT), \
- TRAP(IRQ_S_GEXT), TRAP(IRQ_PMU_OVF), \
- TRAP(EXC_INST_MISALIGNED), TRAP(EXC_INST_ACCESS), TRAP(EXC_INST_ILLEGAL), \
- TRAP(EXC_BREAKPOINT), TRAP(EXC_LOAD_MISALIGNED), TRAP(EXC_LOAD_ACCESS), \
- TRAP(EXC_STORE_MISALIGNED), TRAP(EXC_STORE_ACCESS), TRAP(EXC_SYSCALL), \
- TRAP(EXC_HYPERVISOR_SYSCALL), TRAP(EXC_SUPERVISOR_SYSCALL), \
- TRAP(EXC_INST_PAGE_FAULT), TRAP(EXC_LOAD_PAGE_FAULT), \
- TRAP(EXC_STORE_PAGE_FAULT), TRAP(EXC_INST_GUEST_PAGE_FAULT), \
- TRAP(EXC_LOAD_GUEST_PAGE_FAULT), TRAP(EXC_VIRTUAL_INST_FAULT), \
- TRAP(EXC_STORE_GUEST_PAGE_FAULT)
+ TRAP_IRQ(IRQ_S_SOFT), TRAP_IRQ(IRQ_VS_SOFT), TRAP_IRQ(IRQ_M_SOFT), \
+ TRAP_IRQ(IRQ_S_TIMER), TRAP_IRQ(IRQ_VS_TIMER), TRAP_IRQ(IRQ_M_TIMER), \
+ TRAP_IRQ(IRQ_S_EXT), TRAP_IRQ(IRQ_VS_EXT), TRAP_IRQ(IRQ_M_EXT), \
+ TRAP_IRQ(IRQ_S_GEXT), TRAP_IRQ(IRQ_PMU_OVF), \
+ TRAP_EXC(EXC_INST_MISALIGNED), TRAP_EXC(EXC_INST_ACCESS), TRAP_EXC(EXC_INST_ILLEGAL), \
+ TRAP_EXC(EXC_BREAKPOINT), TRAP_EXC(EXC_LOAD_MISALIGNED), TRAP_EXC(EXC_LOAD_ACCESS), \
+ TRAP_EXC(EXC_STORE_MISALIGNED), TRAP_EXC(EXC_STORE_ACCESS), TRAP_EXC(EXC_SYSCALL), \
+ TRAP_EXC(EXC_HYPERVISOR_SYSCALL), TRAP_EXC(EXC_SUPERVISOR_SYSCALL), \
+ TRAP_EXC(EXC_INST_PAGE_FAULT), TRAP_EXC(EXC_LOAD_PAGE_FAULT), \
+ TRAP_EXC(EXC_STORE_PAGE_FAULT), TRAP_EXC(EXC_INST_GUEST_PAGE_FAULT), \
+ TRAP_EXC(EXC_LOAD_GUEST_PAGE_FAULT), TRAP_EXC(EXC_VIRTUAL_INST_FAULT), \
+ TRAP_EXC(EXC_STORE_GUEST_PAGE_FAULT)
#endif /* ARCH_PERF_RISCV_TRAP_TYPES_H */
--
2.50.1
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Quan Zhou <zhouquan@iscas.ac.cn>,
Anup Patel <anup@brainfault.org>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, guoren@kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH] perf kvm/riscv: Fix event key collision between interrupts and exceptions
Date: Sat, 4 Jul 2026 10:36:08 +0800 [thread overview]
Message-ID: <20260704023608.24971-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
RISC-V scause encodes interrupts and exceptions in the same
cause field, with bit 63 on RV64 and bit 31 on RV32 used to
distinguish interrupts from exceptions. The lower cause bits
overlap between the two namespaces, so masking off the interrupt
bit makes distinct IRQ and exception events map to the same key.
This affects perf kvm stat exit-reason decoding. For example,
IRQ_S_TIMER and EXC_LOAD_ACCESS both use cause code 5, and can be
misreported as the wrong exit reason.
Fix this by using the full scause value as the lookup key in
event_get_key(). Also split TRAP() into TRAP_EXC() and
TRAP_IRQ() so interrupt entries are encoded with the
architecture-specific IRQ bit set, matching the value reported by
hardware.
Fixes: ceea279f9376 ("perf kvm stat: Remove use of the arch directory")
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
.../perf/util/kvm-stat-arch/kvm-stat-riscv.c | 4 +--
.../util/kvm-stat-arch/riscv_trap_types.h | 27 ++++++++++---------
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c b/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c
index 967bba261a47..829096a41a3b 100644
--- a/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c
+++ b/tools/perf/util/kvm-stat-arch/kvm-stat-riscv.c
@@ -23,10 +23,8 @@ static const char * const __kvm_events_tp[] = {
static void event_get_key(struct perf_sample *sample,
struct event_key *key)
{
- int xlen = 64; // TODO: 32-bit support.
-
key->info = 0;
- key->key = perf_sample__intval(sample, kvm_exit_reason(EM_RISCV)) & ~CAUSE_IRQ_FLAG(xlen);
+ key->key = perf_sample__intval(sample, kvm_exit_reason(EM_RISCV));
key->exit_reasons = riscv_exit_reasons;
}
diff --git a/tools/perf/util/kvm-stat-arch/riscv_trap_types.h b/tools/perf/util/kvm-stat-arch/riscv_trap_types.h
index aa5d24fab4ee..da1f1ce55326 100644
--- a/tools/perf/util/kvm-stat-arch/riscv_trap_types.h
+++ b/tools/perf/util/kvm-stat-arch/riscv_trap_types.h
@@ -38,20 +38,21 @@
#define EXC_VIRTUAL_INST_FAULT 22
#define EXC_STORE_GUEST_PAGE_FAULT 23
-#define TRAP(x) { x, #x }
+#define TRAP_EXC(x) { x, #x }
+#define TRAP_IRQ(x) { (x) | CAUSE_IRQ_FLAG(__riscv_xlen), #x }
#define kvm_riscv_trap_class \
- TRAP(IRQ_S_SOFT), TRAP(IRQ_VS_SOFT), TRAP(IRQ_M_SOFT), \
- TRAP(IRQ_S_TIMER), TRAP(IRQ_VS_TIMER), TRAP(IRQ_M_TIMER), \
- TRAP(IRQ_S_EXT), TRAP(IRQ_VS_EXT), TRAP(IRQ_M_EXT), \
- TRAP(IRQ_S_GEXT), TRAP(IRQ_PMU_OVF), \
- TRAP(EXC_INST_MISALIGNED), TRAP(EXC_INST_ACCESS), TRAP(EXC_INST_ILLEGAL), \
- TRAP(EXC_BREAKPOINT), TRAP(EXC_LOAD_MISALIGNED), TRAP(EXC_LOAD_ACCESS), \
- TRAP(EXC_STORE_MISALIGNED), TRAP(EXC_STORE_ACCESS), TRAP(EXC_SYSCALL), \
- TRAP(EXC_HYPERVISOR_SYSCALL), TRAP(EXC_SUPERVISOR_SYSCALL), \
- TRAP(EXC_INST_PAGE_FAULT), TRAP(EXC_LOAD_PAGE_FAULT), \
- TRAP(EXC_STORE_PAGE_FAULT), TRAP(EXC_INST_GUEST_PAGE_FAULT), \
- TRAP(EXC_LOAD_GUEST_PAGE_FAULT), TRAP(EXC_VIRTUAL_INST_FAULT), \
- TRAP(EXC_STORE_GUEST_PAGE_FAULT)
+ TRAP_IRQ(IRQ_S_SOFT), TRAP_IRQ(IRQ_VS_SOFT), TRAP_IRQ(IRQ_M_SOFT), \
+ TRAP_IRQ(IRQ_S_TIMER), TRAP_IRQ(IRQ_VS_TIMER), TRAP_IRQ(IRQ_M_TIMER), \
+ TRAP_IRQ(IRQ_S_EXT), TRAP_IRQ(IRQ_VS_EXT), TRAP_IRQ(IRQ_M_EXT), \
+ TRAP_IRQ(IRQ_S_GEXT), TRAP_IRQ(IRQ_PMU_OVF), \
+ TRAP_EXC(EXC_INST_MISALIGNED), TRAP_EXC(EXC_INST_ACCESS), TRAP_EXC(EXC_INST_ILLEGAL), \
+ TRAP_EXC(EXC_BREAKPOINT), TRAP_EXC(EXC_LOAD_MISALIGNED), TRAP_EXC(EXC_LOAD_ACCESS), \
+ TRAP_EXC(EXC_STORE_MISALIGNED), TRAP_EXC(EXC_STORE_ACCESS), TRAP_EXC(EXC_SYSCALL), \
+ TRAP_EXC(EXC_HYPERVISOR_SYSCALL), TRAP_EXC(EXC_SUPERVISOR_SYSCALL), \
+ TRAP_EXC(EXC_INST_PAGE_FAULT), TRAP_EXC(EXC_LOAD_PAGE_FAULT), \
+ TRAP_EXC(EXC_STORE_PAGE_FAULT), TRAP_EXC(EXC_INST_GUEST_PAGE_FAULT), \
+ TRAP_EXC(EXC_LOAD_GUEST_PAGE_FAULT), TRAP_EXC(EXC_VIRTUAL_INST_FAULT), \
+ TRAP_EXC(EXC_STORE_GUEST_PAGE_FAULT)
#endif /* ARCH_PERF_RISCV_TRAP_TYPES_H */
--
2.50.1
next reply other threads:[~2026-07-04 2:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-04 2:36 fangyu.yu [this message]
2026-07-04 2:36 ` [PATCH] perf kvm/riscv: Fix event key collision between interrupts and exceptions fangyu.yu
2026-07-04 2:44 ` sashiko-bot
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