From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: Chao Liu <chao.liu.zevorn@gmail.com>,
alex.bennee@linaro.org, qemu-s390x@nongnu.org,
Magnus Kulke <magnuskulke@linux.microsoft.com>,
Zhao Liu <zhao1.liu@intel.com>,
qemu-ppc@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Richard Henderson <richard.henderson@linaro.org>,
Mohamed Mediouni <mohamed@unpredictable.fr>,
Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v3 20/32] cpu: Define BreakpointFlags type
Date: Sun, 5 Jul 2026 23:57:16 +0200 [thread overview]
Message-ID: <20260705215729.62196-21-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260705215729.62196-1-philmd@oss.qualcomm.com>
Use the BreakpointFlags typedef to better follow when
we deal with breakpoint flags (BP_*).
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/accel/tcg/cpu-ops.h | 6 ++++--
include/exec/breakpoint.h | 5 +++--
include/exec/watchpoint.h | 6 ++++--
include/hw/core/cpu.h | 4 ++--
accel/tcg/cputlb.c | 12 +++++++-----
accel/tcg/tcg-accel-ops.c | 10 +++++-----
accel/tcg/user-exec-stub.c | 9 +++++----
accel/tcg/watchpoint.c | 9 +++++----
cpu-common.c | 4 ++--
system/watchpoint.c | 4 ++--
target/arm/tcg/debug.c | 4 ++--
target/arm/tcg/mte_helper.c | 3 ++-
target/ppc/cpu.c | 2 +-
target/ppc/kvm.c | 5 +++--
target/riscv/cpu_helper.c | 2 +-
target/riscv/debug.c | 12 +++++-------
target/s390x/tcg/debug.c | 3 ++-
target/xtensa/dbg_helper.c | 2 +-
18 files changed, 56 insertions(+), 46 deletions(-)
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index 710da12b828..f64d94b2b50 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -298,7 +298,8 @@ struct TCGCPUOps {
* specified by @flags. Exit via exception with a hit.
*/
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra);
+ MemTxAttrs attrs, BreakpointFlags flags,
+ uintptr_t ra);
/**
* cpu_watchpoint_address_matches:
@@ -309,7 +310,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
* Return the watchpoint flags that apply to [addr, addr+len).
* If no watchpoint is registered for the range, the result is 0.
*/
-int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
+BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu,
+ vaddr addr, vaddr len);
/*
* Common pointer_wrap implementations.
diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h
index cc6fedd09fe..8ea7147f8c5 100644
--- a/include/exec/breakpoint.h
+++ b/include/exec/breakpoint.h
@@ -12,6 +12,7 @@
#include "exec/vaddr.h"
#include "exec/memattrs.h"
+typedef int BreakpointFlags;
/* Breakpoint/watchpoint flags */
#define BP_MEM_READ 0x01
#define BP_MEM_WRITE 0x02
@@ -28,7 +29,7 @@
typedef struct CPUBreakpoint {
vaddr pc;
- int flags; /* BP_* */
+ BreakpointFlags flags;
QTAILQ_ENTRY(CPUBreakpoint) entry;
} CPUBreakpoint;
@@ -37,7 +38,7 @@ typedef struct CPUWatchpoint {
vaddr len;
vaddr hitaddr;
MemTxAttrs hitattrs;
- int flags; /* BP_* */
+ BreakpointFlags flags;
QTAILQ_ENTRY(CPUWatchpoint) entry;
} CPUWatchpoint;
diff --git a/include/exec/watchpoint.h b/include/exec/watchpoint.h
index c4d069425ba..47f2ad751a4 100644
--- a/include/exec/watchpoint.h
+++ b/include/exec/watchpoint.h
@@ -8,10 +8,12 @@
#ifndef EXEC_WATCHPOINT_H
#define EXEC_WATCHPOINT_H
+#include "exec/breakpoint.h"
+
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint);
+ BreakpointFlags flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
- vaddr len, int flags);
+ vaddr len, BreakpointFlags flags);
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e5b68bced3d..e70cd8239fb 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1138,9 +1138,9 @@ void qemu_init_vcpu(CPUState *cpu);
*/
void cpu_single_step(CPUState *cpu, int enabled);
-int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
+int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags,
CPUBreakpoint **breakpoint);
-int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
+int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags);
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 7f7c208ba12..e2911e3aac6 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1033,7 +1033,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
CPUTLBEntry *te, tn;
hwaddr iotlb, xlat, sz, paddr_page;
vaddr addr_page;
- int asidx, wp_flags, prot;
+ int asidx, prot;
+ BreakpointFlags wp_flags;
bool is_ram, is_romd;
assert_cpu_is_self(cpu);
@@ -1499,8 +1500,8 @@ void *probe_access(CPUArchState *env, vaddr addr, int size,
if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
/* Handle watchpoints. */
if (flags & TLB_WATCHPOINT) {
- int wp_access = (access_type == MMU_DATA_STORE
- ? BP_MEM_WRITE : BP_MEM_READ);
+ BreakpointFlags wp_access = (access_type == MMU_DATA_STORE
+ ? BP_MEM_WRITE : BP_MEM_READ);
cpu_check_watchpoint(env_cpu(env), addr, size,
full->attrs, wp_access, retaddr);
}
@@ -1702,7 +1703,8 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMULookupPageData *data,
/* On watchpoint hit, this will longjmp out. */
if (flags & TLB_WATCHPOINT) {
- int wp = access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ;
+ BreakpointFlags wp = access_type == MMU_DATA_STORE ? BP_MEM_WRITE
+ : BP_MEM_READ;
cpu_check_watchpoint(cpu, addr, size, full->attrs, wp, ra);
flags &= ~TLB_WATCHPOINT;
}
@@ -1885,7 +1887,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi,
}
if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
- int wp_flags = 0;
+ BreakpointFlags wp_flags = 0;
if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) {
wp_flags |= BP_MEM_WRITE;
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 927af6c1db0..26d34c72d9a 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -110,20 +110,20 @@ void tcg_handle_interrupt(CPUState *cpu, int mask)
}
/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */
-static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
+static inline BreakpointFlags xlat_gdb_type(CPUState *cpu, int gdbtype)
{
- static const int xlat[] = {
+ static const BreakpointFlags xlat[] = {
[GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
[GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
[GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
};
- int cputype = xlat[gdbtype];
+ BreakpointFlags cpuflags = xlat[gdbtype];
if (cpu->cc->gdb_stop_before_watchpoint) {
- cputype |= BP_STOP_BEFORE_ACCESS;
+ cpuflags |= BP_STOP_BEFORE_ACCESS;
}
- return cputype;
+ return cpuflags;
}
static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c
index 28286e11a60..6cfb317ed0f 100644
--- a/accel/tcg/user-exec-stub.c
+++ b/accel/tcg/user-exec-stub.c
@@ -22,13 +22,13 @@ void cpu_exec_reset_hold(CPUState *cpu)
}
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint)
+ BreakpointFlags flags, CPUWatchpoint **watchpoint)
{
return -ENOSYS;
}
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
- vaddr len, int flags)
+ vaddr len, BreakpointFlags flags)
{
return -ENOSYS;
}
@@ -41,13 +41,14 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
{
}
-int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
+BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu,
+ vaddr addr, vaddr len)
{
return 0;
}
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs atr, int fl, uintptr_t ra)
+ MemTxAttrs atr, BreakpointFlags flags, uintptr_t ra)
{
}
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index c75ed278459..5ea66e9763a 100644
--- a/accel/tcg/watchpoint.c
+++ b/accel/tcg/watchpoint.c
@@ -52,10 +52,11 @@ static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
}
/* Return flags for watchpoints that match addr + prot. */
-int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
+BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu,
+ vaddr addr, vaddr len)
{
CPUWatchpoint *wp;
- int ret = 0;
+ BreakpointFlags ret = 0;
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)) {
@@ -67,7 +68,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
/* Generate a debug exception if a watchpoint has been hit. */
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra)
+ MemTxAttrs attrs, BreakpointFlags flags, uintptr_t ra)
{
CPUWatchpoint *wp;
@@ -91,7 +92,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
assert((flags & ~BP_MEM_ACCESS) == 0);
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- int hit_flags = wp->flags & flags;
+ BreakpointFlags hit_flags = wp->flags & flags;
if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
if (replay_running_debug()) {
diff --git a/cpu-common.c b/cpu-common.c
index adb76b3a786..600cd56dd0e 100644
--- a/cpu-common.c
+++ b/cpu-common.c
@@ -404,7 +404,7 @@ bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
}
/* Add a breakpoint. */
-int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
+int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags,
CPUBreakpoint **breakpoint)
{
CPUBreakpoint *bp;
@@ -434,7 +434,7 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
}
/* Remove a specific breakpoint. */
-int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
+int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags)
{
CPUBreakpoint *bp;
diff --git a/system/watchpoint.c b/system/watchpoint.c
index 21d0bb36cae..41d188d7cdd 100644
--- a/system/watchpoint.c
+++ b/system/watchpoint.c
@@ -26,7 +26,7 @@
/* Add a watchpoint. */
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
- int flags, CPUWatchpoint **watchpoint)
+ BreakpointFlags flags, CPUWatchpoint **watchpoint)
{
CPUWatchpoint *wp;
vaddr in_page;
@@ -65,7 +65,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
/* Remove a specific watchpoint. */
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
- int flags)
+ BreakpointFlags flags)
{
CPUWatchpoint *wp;
diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c
index 07a52643e71..11043ecd589 100644
--- a/target/arm/tcg/debug.c
+++ b/target/arm/tcg/debug.c
@@ -550,7 +550,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
vaddr wvr = env->cp15.dbgwvr[n];
uint64_t wcr = env->cp15.dbgwcr[n];
int mask;
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
+ BreakpointFlags flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
if (env->cpu_watchpoint[n]) {
cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
@@ -656,7 +656,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
uint64_t bcr = env->cp15.dbgbcr[n];
vaddr addr;
int bt;
- int flags = BP_CPU;
+ BreakpointFlags flags = BP_CPU;
if (env->cpu_breakpoint[n]) {
cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index dca4ef5a942..17f920b3f35 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -190,7 +190,8 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx,
/* Any debug exception has priority over a tag check exception. */
if (!probe && unlikely(flags & TLB_WATCHPOINT)) {
- int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
+ BreakpointFlags wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ
+ : BP_MEM_WRITE;
assert(ra != 0);
cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra);
}
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 41edb18643d..913920d55b8 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -145,7 +145,7 @@ void ppc_update_daw(CPUPPCState *env, int rid)
bool sv = extract32(dawrx, PPC_BIT_NR(62), 1);
bool pr = extract32(dawrx, PPC_BIT_NR(62), 1);
vaddr len;
- int flags;
+ BreakpointFlags flags;
if (env->dawr_watchpoint[rid]) {
cpu_watchpoint_remove_by_ref(cs, env->dawr_watchpoint[rid]);
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index b94c2997a07..2a3711fb1df 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1429,7 +1429,7 @@ static int find_hw_breakpoint(target_ulong addr, int type)
return -1;
}
-static int find_hw_watchpoint(target_ulong addr, int *flag)
+static int find_hw_watchpoint(target_ulong addr, BreakpointFlags *flag)
{
int n;
@@ -1575,7 +1575,6 @@ static int kvm_handle_hw_breakpoint(CPUState *cs,
{
int handle = DEBUG_RETURN_GUEST;
int n;
- int flag = 0;
if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
@@ -1585,6 +1584,8 @@ static int kvm_handle_hw_breakpoint(CPUState *cs,
}
} else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
KVMPPC_DEBUG_WATCH_WRITE)) {
+ BreakpointFlags flag = 0;
+
n = find_hw_watchpoint(arch_info->address, &flag);
if (n >= 0) {
handle = DEBUG_RETURN_GDB;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2db07f5dfb6..c318dcd633c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -2000,7 +2000,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else if (probe) {
return false;
} else {
- int wp_access = 0;
+ BreakpointFlags wp_access = 0;
if (access_type == MMU_DATA_LOAD) {
wp_access |= BP_MEM_READ;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index ba5bc6ae13d..082ced71bb7 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -480,7 +480,7 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
target_ulong addr = env->tdata2[index];
bool enabled = type2_breakpoint_enabled(ctrl);
CPUState *cs = env_cpu(env);
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
+ BreakpointFlags flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t size, def_size;
if (!enabled) {
@@ -605,7 +605,7 @@ static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index)
target_ulong addr = env->tdata2[index];
bool enabled = type6_breakpoint_enabled(ctrl);
CPUState *cs = env_cpu(env);
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
+ BreakpointFlags flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t size;
if (!enabled) {
@@ -993,12 +993,10 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
CPURISCVState *env = &cpu->env;
target_ulong ctrl;
target_ulong addr;
- int trigger_type;
- int flags;
- int i;
- for (i = 0; i < env->num_triggers; i++) {
- trigger_type = get_trigger_type(env, i);
+ for (int i = 0; i < env->num_triggers; i++) {
+ int trigger_type = get_trigger_type(env, i);
+ BreakpointFlags flags;
if (!trigger_common_match(env, trigger_type, i)) {
continue;
diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c
index 99140b1ac9a..d10e9ed8922 100644
--- a/target/s390x/tcg/debug.c
+++ b/target/s390x/tcg/debug.c
@@ -14,7 +14,8 @@
void s390_cpu_recompute_watchpoints(CPUState *cs)
{
- const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
+ const BreakpointFlags wp_flags = BP_CPU | BP_MEM_WRITE
+ | BP_STOP_BEFORE_ACCESS;
CPUS390XState *env = cpu_env(cs);
/* We are called when the watchpoints have changed. First
diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
index 3b91f7c38ac..990012f60e6 100644
--- a/target/xtensa/dbg_helper.c
+++ b/target/xtensa/dbg_helper.c
@@ -85,7 +85,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
uint32_t dbreakc)
{
CPUState *cs = env_cpu(env);
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
+ BreakpointFlags flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t mask = dbreakc | ~DBREAKC_MASK;
if (env->cpu_watchpoint[i]) {
--
2.53.0
next prev parent reply other threads:[~2026-07-05 22:00 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-05 21:56 [PATCH v3 00/32] accel: Unassorted cleanups around debugging Philippe Mathieu-Daudé
2026-07-05 21:56 ` [PATCH v3 01/32] cpu: Constify CPUState::cc (cached CPUClass pointer) Philippe Mathieu-Daudé
2026-07-05 21:56 ` [PATCH v3 02/32] target/i386: Remove duplicate tlb_flush() call in cpu_post_load() Philippe Mathieu-Daudé
2026-07-05 21:56 ` [PATCH v3 03/32] accel/tcg: Restrict tlb_protect/unprotect_code() to TCG Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 04/32] accel/hvf: Remove left-over comment Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 05/32] accel/mshv: Replace @dirty field by generic CPUState::vcpu_dirty field Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 06/32] gdbstub: Add trace event for STEP packet handler Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 07/32] gdbstub: Only return E22 when reverse GDB is not supported Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 08/32] accel/whpx: Implement missing AccelClass::gdbstub_supported_sstep_flags Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 09/32] accel/kvm: Always define AccelOpsClass::supports_guest_debug Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 10/32] accel/kvm: Simplify kvm_init() w.r.t. TARGET_KVM_HAVE_GUEST_DEBUG Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 11/32] accel/kvm: Hold have_guest_debug in KVMState Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 12/32] gdbstub: Reduce gdb_supports_guest_debug() scope Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 13/32] gdbstub: Move supported_sstep_flags in AccelGdbConfig structure Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 14/32] accel: Have each implementation return their AccelGdbConfig Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 15/32] gdbstub: Make default replay_mode value explicit in stubs Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 16/32] accel: Hold @can_reverse information in AccelGdbConfig Philippe Mathieu-Daudé
2026-07-06 8:59 ` Manos Pitsidianakis
2026-07-05 21:57 ` [PATCH v3 17/32] accel: Remove AccelOpsClass::supports_guest_debug Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 18/32] cpu: Move cpu_breakpoint_test out of line Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 19/32] cpu: Move BREAKPOINT definitions to 'exec/breakpoint.h' Philippe Mathieu-Daudé
2026-07-05 21:57 ` Philippe Mathieu-Daudé [this message]
2026-07-05 21:57 ` [PATCH v3 21/32] accel: Remove unnecessary 'inline' qualifier in remove_all_breakpoints Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 22/32] gdbstub/user: Directly call gdb_breakpoint_remove_all() in user mode Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 23/32] gdbstub: Reduce @type variable scope Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 24/32] gdbstub: Introduce GdbBreakpointType enumerator Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 25/32] accel: Use GdbBreakpointType enum Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 26/32] target/arm: Inline check_watchpoints() in arm_debug_check_watchpoint() Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 27/32] target/ppc: Ensure TCG is used in ppc_update_daw() Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 28/32] accel/tcg: Improve docstrings around TCGCPUOps::*watchpoint* handlers Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 29/32] cpu: Better name cpu_single_step() trace event Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 30/32] cpu: Introduce cpu_single_stepping() helper Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 31/32] cpu: Rename CPUState @singlestep_enabled -> @singlestep_flags Philippe Mathieu-Daudé
2026-07-05 21:57 ` [PATCH v3 32/32] cpu: Only check SSTEP_ENABLE flag in cpu_single_stepping() Philippe Mathieu-Daudé
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