From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kathiravan T <quic_kathirav@quicinc.com>,
Baruch Siach <baruch@tkos.co.il>,
Dmitry Baryshkov <lumag@kernel.org>,
Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>,
Manu Gautam <mgautam@codeaurora.org>,
Kishon Vijay Abraham I <kishon@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/3] phy: qcom-qusb2: describe autoresume bit
Date: Mon, 06 Jul 2026 16:53:16 +0300 [thread overview]
Message-ID: <20260706-fix-qusb2-v2-3-8d9cd73b1db7@oss.qualcomm.com> (raw)
In-Reply-To: <20260706-fix-qusb2-v2-0-8d9cd73b1db7@oss.qualcomm.com>
There is a confusion regarding the autoresume bit. Some verions of the
QUSB2 PHY have it in the TEST1 register, while on the others it is a
part of the TEST_CTRL register. When adding support for autoresume bit,
the code attempted to simplify the handling of those registers, putting
both registers to the TEST1 layout entry. In the end,
ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
(because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
layout entry.
Update the platform data to specify the register to be used for
autoresume handling, define both TEST1 and TEST_CTRL registers and merge
ipq6018_regs_layout and msm8996_regs_layout which become identical
afterwards.
Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 48 +++++++++++++++--------------------
1 file changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index b1d34b080cfd..b22b3c6adfd3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -131,8 +131,13 @@ enum qusb2phy_reg_layout {
QUSB2PHY_PORT_TUNE5,
QUSB2PHY_PORT_TEST1,
QUSB2PHY_PORT_TEST2,
+ QUSB2PHY_PORT_TEST_CTRL,
QUSB2PHY_PORT_POWERDOWN,
QUSB2PHY_INTR_CTRL,
+
+ /* layout of the autoresume bit */
+ QUSB2PHY_AUTORESUME_REG,
+ QUSB2PHY_AUTORESUME_BIT,
};
static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
@@ -164,19 +169,6 @@ static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
};
-static const unsigned int ipq6018_regs_layout[] = {
- [QUSB2PHY_PLL_STATUS] = 0x38,
- [QUSB2PHY_PORT_TUNE1] = 0x80,
- [QUSB2PHY_PORT_TUNE2] = 0x84,
- [QUSB2PHY_PORT_TUNE3] = 0x88,
- [QUSB2PHY_PORT_TUNE4] = 0x8C,
- [QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0x98,
- [QUSB2PHY_PORT_TEST2] = 0x9C,
- [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
- [QUSB2PHY_INTR_CTRL] = 0xBC,
-};
-
static const unsigned int msm8996_regs_layout[] = {
[QUSB2PHY_PLL_STATUS] = 0x38,
[QUSB2PHY_PORT_TUNE1] = 0x80,
@@ -184,10 +176,14 @@ static const unsigned int msm8996_regs_layout[] = {
[QUSB2PHY_PORT_TUNE3] = 0x88,
[QUSB2PHY_PORT_TUNE4] = 0x8c,
[QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0xb8,
+ [QUSB2PHY_PORT_TEST1] = 0x98,
[QUSB2PHY_PORT_TEST2] = 0x9c,
+ [QUSB2PHY_PORT_TEST_CTRL] = 0xb8,
[QUSB2PHY_PORT_POWERDOWN] = 0xb4,
[QUSB2PHY_INTR_CTRL] = 0xbc,
+
+ [QUSB2PHY_AUTORESUME_REG] = 0xb8, /* TEST_CTRL */
+ [QUSB2PHY_AUTORESUME_BIT] = BIT(3),
};
static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
@@ -217,6 +213,9 @@ static const unsigned int msm8998_regs_layout[] = {
[QUSB2PHY_PORT_TEST2] = 0x250,
[QUSB2PHY_PORT_POWERDOWN] = 0x210,
[QUSB2PHY_INTR_CTRL] = 0x22c,
+
+ [QUSB2PHY_AUTORESUME_REG] = 0x24c, /* TEST1 */
+ [QUSB2PHY_AUTORESUME_BIT] = BIT(0),
};
static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
@@ -259,6 +258,9 @@ static const unsigned int qusb2_v2_regs_layout[] = {
[QUSB2PHY_PORT_TEST2] = 0x258,
[QUSB2PHY_PORT_POWERDOWN] = 0x210,
[QUSB2PHY_INTR_CTRL] = 0x230,
+
+ [QUSB2PHY_AUTORESUME_REG] = 0x254, /* TEST1 */
+ [QUSB2PHY_AUTORESUME_BIT] = BIT(0),
};
static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
@@ -293,7 +295,6 @@ struct qusb2_phy_cfg {
const unsigned int *regs;
unsigned int mask_core_ready;
unsigned int disable_ctrl;
- unsigned int autoresume_en;
bool autoresume_disable;
/* true if PHY has PLL_TEST register to select clk_scheme */
@@ -318,7 +319,6 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
.se_clk_scheme_default = true,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg msm8998_phy_cfg = {
@@ -330,20 +330,18 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.se_clk_scheme_default = true,
- .autoresume_en = BIT(0),
.update_tune1_with_efuse = true,
};
static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
.tbl = ipq6018_init_tbl,
.tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
- .regs = ipq6018_regs_layout,
+ .regs = msm8996_regs_layout,
.disable_ctrl = POWER_DOWN,
.mask_core_ready = PLL_LOCKED,
/* autoresume not used */
.autoresume_disable = true,
- .autoresume_en = BIT(0),
};
static const struct qusb2_phy_cfg qcs615_phy_cfg = {
@@ -353,7 +351,6 @@ static const struct qusb2_phy_cfg qcs615_phy_cfg = {
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
@@ -366,7 +363,6 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.se_clk_scheme_default = true,
- .autoresume_en = BIT(0),
.update_tune1_with_efuse = true,
};
@@ -379,7 +375,6 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
.se_clk_scheme_default = false,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg sm6115_phy_cfg = {
@@ -391,7 +386,6 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg = {
.se_clk_scheme_default = true,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const char * const qusb2_phy_vreg_names[] = {
@@ -679,11 +673,11 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
/* enable phy auto-resume only if device is connected on bus */
if (qphy->mode != PHY_MODE_INVALID && !cfg->autoresume_disable) {
- qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
- cfg->autoresume_en);
+ unsigned int reg = cfg->regs[QUSB2PHY_AUTORESUME_REG];
+
+ qusb2_setbits(qphy->base, reg, cfg->regs[QUSB2PHY_AUTORESUME_BIT]);
/* Autoresume bit has to be toggled in order to enable it */
- qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
- cfg->autoresume_en);
+ qusb2_clrbits(qphy->base, reg, cfg->regs[QUSB2PHY_AUTORESUME_BIT]);
}
if (!qphy->has_se_clk_scheme)
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kathiravan T <quic_kathirav@quicinc.com>,
Baruch Siach <baruch@tkos.co.il>,
Dmitry Baryshkov <lumag@kernel.org>,
Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>,
Manu Gautam <mgautam@codeaurora.org>,
Kishon Vijay Abraham I <kishon@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/3] phy: qcom-qusb2: describe autoresume bit
Date: Mon, 06 Jul 2026 16:53:16 +0300 [thread overview]
Message-ID: <20260706-fix-qusb2-v2-3-8d9cd73b1db7@oss.qualcomm.com> (raw)
In-Reply-To: <20260706-fix-qusb2-v2-0-8d9cd73b1db7@oss.qualcomm.com>
There is a confusion regarding the autoresume bit. Some verions of the
QUSB2 PHY have it in the TEST1 register, while on the others it is a
part of the TEST_CTRL register. When adding support for autoresume bit,
the code attempted to simplify the handling of those registers, putting
both registers to the TEST1 layout entry. In the end,
ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
(because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
layout entry.
Update the platform data to specify the register to be used for
autoresume handling, define both TEST1 and TEST_CTRL registers and merge
ipq6018_regs_layout and msm8996_regs_layout which become identical
afterwards.
Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 48 +++++++++++++++--------------------
1 file changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index b1d34b080cfd..b22b3c6adfd3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -131,8 +131,13 @@ enum qusb2phy_reg_layout {
QUSB2PHY_PORT_TUNE5,
QUSB2PHY_PORT_TEST1,
QUSB2PHY_PORT_TEST2,
+ QUSB2PHY_PORT_TEST_CTRL,
QUSB2PHY_PORT_POWERDOWN,
QUSB2PHY_INTR_CTRL,
+
+ /* layout of the autoresume bit */
+ QUSB2PHY_AUTORESUME_REG,
+ QUSB2PHY_AUTORESUME_BIT,
};
static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
@@ -164,19 +169,6 @@ static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
};
-static const unsigned int ipq6018_regs_layout[] = {
- [QUSB2PHY_PLL_STATUS] = 0x38,
- [QUSB2PHY_PORT_TUNE1] = 0x80,
- [QUSB2PHY_PORT_TUNE2] = 0x84,
- [QUSB2PHY_PORT_TUNE3] = 0x88,
- [QUSB2PHY_PORT_TUNE4] = 0x8C,
- [QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0x98,
- [QUSB2PHY_PORT_TEST2] = 0x9C,
- [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
- [QUSB2PHY_INTR_CTRL] = 0xBC,
-};
-
static const unsigned int msm8996_regs_layout[] = {
[QUSB2PHY_PLL_STATUS] = 0x38,
[QUSB2PHY_PORT_TUNE1] = 0x80,
@@ -184,10 +176,14 @@ static const unsigned int msm8996_regs_layout[] = {
[QUSB2PHY_PORT_TUNE3] = 0x88,
[QUSB2PHY_PORT_TUNE4] = 0x8c,
[QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0xb8,
+ [QUSB2PHY_PORT_TEST1] = 0x98,
[QUSB2PHY_PORT_TEST2] = 0x9c,
+ [QUSB2PHY_PORT_TEST_CTRL] = 0xb8,
[QUSB2PHY_PORT_POWERDOWN] = 0xb4,
[QUSB2PHY_INTR_CTRL] = 0xbc,
+
+ [QUSB2PHY_AUTORESUME_REG] = 0xb8, /* TEST_CTRL */
+ [QUSB2PHY_AUTORESUME_BIT] = BIT(3),
};
static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
@@ -217,6 +213,9 @@ static const unsigned int msm8998_regs_layout[] = {
[QUSB2PHY_PORT_TEST2] = 0x250,
[QUSB2PHY_PORT_POWERDOWN] = 0x210,
[QUSB2PHY_INTR_CTRL] = 0x22c,
+
+ [QUSB2PHY_AUTORESUME_REG] = 0x24c, /* TEST1 */
+ [QUSB2PHY_AUTORESUME_BIT] = BIT(0),
};
static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
@@ -259,6 +258,9 @@ static const unsigned int qusb2_v2_regs_layout[] = {
[QUSB2PHY_PORT_TEST2] = 0x258,
[QUSB2PHY_PORT_POWERDOWN] = 0x210,
[QUSB2PHY_INTR_CTRL] = 0x230,
+
+ [QUSB2PHY_AUTORESUME_REG] = 0x254, /* TEST1 */
+ [QUSB2PHY_AUTORESUME_BIT] = BIT(0),
};
static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
@@ -293,7 +295,6 @@ struct qusb2_phy_cfg {
const unsigned int *regs;
unsigned int mask_core_ready;
unsigned int disable_ctrl;
- unsigned int autoresume_en;
bool autoresume_disable;
/* true if PHY has PLL_TEST register to select clk_scheme */
@@ -318,7 +319,6 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
.se_clk_scheme_default = true,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg msm8998_phy_cfg = {
@@ -330,20 +330,18 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.se_clk_scheme_default = true,
- .autoresume_en = BIT(0),
.update_tune1_with_efuse = true,
};
static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
.tbl = ipq6018_init_tbl,
.tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
- .regs = ipq6018_regs_layout,
+ .regs = msm8996_regs_layout,
.disable_ctrl = POWER_DOWN,
.mask_core_ready = PLL_LOCKED,
/* autoresume not used */
.autoresume_disable = true,
- .autoresume_en = BIT(0),
};
static const struct qusb2_phy_cfg qcs615_phy_cfg = {
@@ -353,7 +351,6 @@ static const struct qusb2_phy_cfg qcs615_phy_cfg = {
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
@@ -366,7 +363,6 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.se_clk_scheme_default = true,
- .autoresume_en = BIT(0),
.update_tune1_with_efuse = true,
};
@@ -379,7 +375,6 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
.se_clk_scheme_default = false,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const struct qusb2_phy_cfg sm6115_phy_cfg = {
@@ -391,7 +386,6 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg = {
.se_clk_scheme_default = true,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
- .autoresume_en = BIT(3),
};
static const char * const qusb2_phy_vreg_names[] = {
@@ -679,11 +673,11 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
/* enable phy auto-resume only if device is connected on bus */
if (qphy->mode != PHY_MODE_INVALID && !cfg->autoresume_disable) {
- qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
- cfg->autoresume_en);
+ unsigned int reg = cfg->regs[QUSB2PHY_AUTORESUME_REG];
+
+ qusb2_setbits(qphy->base, reg, cfg->regs[QUSB2PHY_AUTORESUME_BIT]);
/* Autoresume bit has to be toggled in order to enable it */
- qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
- cfg->autoresume_en);
+ qusb2_clrbits(qphy->base, reg, cfg->regs[QUSB2PHY_AUTORESUME_BIT]);
}
if (!qphy->has_se_clk_scheme)
--
2.47.3
next prev parent reply other threads:[~2026-07-06 13:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 13:53 [PATCH v2 0/3] phy: qcom-qusb2: sort out register layouts Dmitry Baryshkov
2026-07-06 13:53 ` Dmitry Baryshkov
2026-07-06 13:53 ` [PATCH v2 1/3] phy: qcom-qusb2: enable autoresume on Talos platforms Dmitry Baryshkov
2026-07-06 13:53 ` Dmitry Baryshkov
2026-07-06 15:37 ` Konrad Dybcio
2026-07-06 15:37 ` Konrad Dybcio
2026-07-06 13:53 ` [PATCH v2 2/3] phy: qcom-qusb2: correst PHY description for IPQ6018 Dmitry Baryshkov
2026-07-06 13:53 ` Dmitry Baryshkov
2026-07-07 7:39 ` Konrad Dybcio
2026-07-07 7:39 ` Konrad Dybcio
2026-07-06 13:53 ` Dmitry Baryshkov [this message]
2026-07-06 13:53 ` [PATCH v2 3/3] phy: qcom-qusb2: describe autoresume bit Dmitry Baryshkov
2026-07-07 8:43 ` [PATCH v2 0/3] phy: qcom-qusb2: sort out register layouts Konrad Dybcio
2026-07-07 8:43 ` Konrad Dybcio
2026-09-09 16:17 ` Manivannan Sadhasivam
2026-09-13 6:22 ` Vinod Koul
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