Re: [PATCH v2 3/4] arm64: dts: rockchip: Add crypto node to rk356x-base

From: Dawid Olesinski <dawidro@gmail.com>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: Sebastian Reichel <sebastian.reichel@collabora.com>,
	Herbert Xu <herbert@gondor.apana.org.au>,
	"David S . Miller" <davem@davemloft.net>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Corentin Labbe <clabbe@baylibre.com>,
	linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/4] arm64: dts: rockchip: Add crypto node to rk356x-base
Date: Fri, 10 Jul 2026 15:30:12 +0100	[thread overview]
Message-ID: <20260710153012.0a840512@enyo> (raw)
In-Reply-To: <4011768.FjKLVJYuhi@diego>

On Thu, 09 Jul 2026 09:07:23 +0200
Heiko Stübner <heiko@sntech.de> wrote:

> Am Donnerstag, 9. Juli 2026, 01:56:10 Mitteleuropäische Sommerzeit
> schrieb Sebastian Reichel:
> > Hi,
> > 
> > On Wed, Jul 08, 2026 at 06:58:24PM +0100, Dawid Olesinski wrote:  
> > > Add the device tree node for the V2 cryptographic hardware
> > > accelerator on RK356x SoCs (RK3566, RK3568).
> > > 
> > > The IP block sits in the non-secure peripheral domain. Its three
> > > clocks (core, aclk, hclk) and reset line are accessible directly
> > > through the main non-secure CRU, so no firmware intermediary is
> > > required.
> > > 
> > > The node is disabled by default; board files that wish to use
> > > hardware crypto offload must enable it.  
> > 
> > Why is it disabled by default? It doesn't seem to be board specific
> > at all to me (the same question applies to the RK3588 DT).  
> 
> You're definitly right about that ... there are no board specific
> resources needed, so Dawid please drop the status from both nodes.
> 
> 
> Heiko
> 

I'll drop the `status = "disabled";` 
lines from both the RK356x and RK3588 device trees in v3.

Thanks for the review!

Dawid

> > > 
> > > Signed-off-by: Dawid Olesinski <dawidro@gmail.com>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++
> > >  1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> > > b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index
> > > a5832895bd39..9de7e7487ca1 100644 ---
> > > a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++
> > > b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1112,6
> > > +1112,18 @@ sdhci: mmc@fe310000 { status = "disabled";
> > >  	};
> > >  
> > > +	crypto: crypto@fe380000 {
> > > +		compatible = "rockchip,rk3568-crypto";
> > > +		reg = <0x0 0xfe380000 0x0 0x2000>;
> > > +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > > +		clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru
> > > ACLK_CRYPTO_NS>,
> > > +			 <&cru HCLK_CRYPTO_NS>;
> > > +		clock-names = "core", "aclk", "hclk";
> > > +		resets = <&cru SRST_CRYPTO_NS_CORE>;
> > > +		reset-names = "core";
> > > +		status = "disabled";
> > > +	};
> > > +
> > >  	/*
> > >  	 * Testing showed that the HWRNG found in RK3566
> > > produces unacceptably
> > >  	 * low quality of random data, so the HWRNG isn't
> > > enabled for all RK356x  
> >   
> 
> 
> 
> 