From: sashiko-bot@kernel.org
To: "Stefano Radaelli" <stefano.radaelli21@gmail.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v3 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
Date: Fri, 10 Jul 2026 17:50:09 +0000 [thread overview]
Message-ID: <20260710175010.258CD1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <3f58a10e07d9a353c7c18f7d3ec8ea1f4c08f4f0.1783689915.git.stefano.r@variscite.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The PCA9534 I2C GPIO expander interrupt is configured as edge-triggered (IRQ_TYPE_EDGE_FALLING) instead of level-triggered (IRQ_TYPE_LEVEL_LOW), which will lead to permanently missed interrupts.
--
--- Patch [3]: [PATCH v3 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board ---
commit bd58b379bc670274a1ca977bcbbbb50a0e0f09a6
Author: Stefano Radaelli <stefano.r@variscite.com>
arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
This commit adds device tree support for the Variscite Symphony carrier
board with the VAR-SOM-AM62 system on module.
Link: https://www.variscite.it/product/single-board-computers/symphony-board/
> diff --git a/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts
> new file mode 100644
> index 0000000000000..e2fba95d9b948
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts
[ ... ]
> +&main_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c0>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + /* GPIO expander */
> + pca9534: gpio@20 {
> + compatible = "nxp,pca9534";
> + reg = <0x20>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pca9534>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&main_gpio1>;
> + interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
[Severity: Medium]
Will this edge-triggered configuration cause permanently missed interrupts?
The PCA9534 INT output is an open-drain active-low signal that remains low
as long as unhandled interrupt events exist. If a new GPIO event occurs
while the CPU is processing a previous interrupt (like a rapid subsequent
button press or a contact bounce on the configured gpio-keys), the INT
line will stay logically low.
Because the interrupt controller is configured for EDGE_FALLING, it won't
detect the subsequent event without a new falling edge, leaving the input
device stuck and unresponsive.
Should this be configured as IRQ_TYPE_LEVEL_LOW instead?
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1783689915.git.stefano.r@variscite.com?part=3
prev parent reply other threads:[~2026-07-10 17:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 17:43 [PATCH v3 0/3] Add support for Variscite VAR-SOM-AM62 and Symphony board Stefano Radaelli
2026-07-10 17:43 ` [PATCH v3 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62 Stefano Radaelli
2026-07-10 21:41 ` Rob Herring
2026-07-12 13:58 ` Stefano Radaelli
2026-07-10 17:43 ` [PATCH v3 2/3] arm64: dts: ti: Add support " Stefano Radaelli
2026-07-10 17:55 ` sashiko-bot
2026-07-10 17:43 ` [PATCH v3 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board Stefano Radaelli
2026-07-10 17:50 ` sashiko-bot [this message]
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