From: Stefano Radaelli <stefano.radaelli21@gmail.com>
To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: pierluigi.p@variscite.com, matthias.p@variscite.com,
Stefano Radaelli <stefano.r@variscite.com>,
Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Kees Cook <kees@kernel.org>,
Tony Luck <tony.luck@intel.com>,
"Guilherme G. Piccoli" <gpiccoli@igalia.com>
Subject: [PATCH v3 0/3] Add support for Variscite VAR-SOM-AM62 and Symphony board
Date: Fri, 10 Jul 2026 19:43:06 +0200 [thread overview]
Message-ID: <cover.1783689915.git.stefano.r@variscite.com> (raw)
The series includes:
- Device tree bindings documentation
- SOM device tree with common peripherals
- Symphony carrier board device tree with board-specific features
The implementation follows the standard SOM + carrier board pattern
where the SOM dtsi contains only peripherals mounted on the module,
while carrier-specific interfaces are enabled in the board dts.
v2->v3:
- Add audio_refclk1 clock
- Removed pinctrl_vdd_mmc2
- Fix reg_sdhc1_vmmc regulator
- Add missing properties on pca9534 node
v1->v2:
- Fix AM62X_MCU_IOPAD macro
- Fix OPP table comment
- Remove reg_vdd_mmc2 regulator
- Fix reg_sdhc1_vmmc pinctrl
- Add reg_ov5640_buf_en pinctrl
Stefano Radaelli (3):
dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62
arm64: dts: ti: Add support for Variscite VAR-SOM-AM62
arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
.../devicetree/bindings/arm/ti/k3.yaml | 6 +
arch/arm64/boot/dts/ti/Makefile | 1 +
.../boot/dts/ti/k3-am625-var-som-symphony.dts | 555 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi | 483 +++++++++++++++
4 files changed, 1045 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi
base-commit: 5c73cd9f0819c1c44e373e3dabb68318b1de1a12
--
2.47.3
next reply other threads:[~2026-07-10 17:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 17:43 Stefano Radaelli [this message]
2026-07-10 17:43 ` [PATCH v3 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62 Stefano Radaelli
2026-07-10 21:41 ` Rob Herring
2026-07-12 13:58 ` Stefano Radaelli
2026-07-10 17:43 ` [PATCH v3 2/3] arm64: dts: ti: Add support " Stefano Radaelli
2026-07-10 17:55 ` sashiko-bot
2026-07-10 17:43 ` [PATCH v3 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board Stefano Radaelli
2026-07-10 17:50 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1783689915.git.stefano.r@variscite.com \
--to=stefano.radaelli21@gmail.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=gpiccoli@igalia.com \
--cc=kees@kernel.org \
--cc=kristo@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=matthias.p@variscite.com \
--cc=nm@ti.com \
--cc=pierluigi.p@variscite.com \
--cc=robh@kernel.org \
--cc=stefano.r@variscite.com \
--cc=tony.luck@intel.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.