Re: [PATCH v3 1/5] iommu/arm-smmu-v3-iommufd: Reject unsupported bits in invalidation commands

[Jason Gunthorpe <jgg@nvidia.com>]

On Tue, Jul 14, 2026 at 09:35:25AM +0000, Pranjal Shrivastava wrote:
> > +	u8 ttl = FIELD_GET(CMDQ_TLBI_1_TTL, cmd->cmd.data[1]);
> > +	u8 tg = FIELD_GET(CMDQ_TLBI_1_TG, cmd->cmd.data[1]);
> > +
> > +	/* NUM, SCALE and TTL are RES0 when TG == 0 */
> > +	if (!tg)
> > +		return (range || ttl) ? -EIO : 0;
> > +	/* TTL == 0b01 with a 16KB TG requires SMMU_IDR5.DS */
> > +	if (tg == 2 && ttl == 1 && !(smmu->features & ARM_SMMU_FEAT_DS))
> 
> I agree we must check this but I'm a little confused, How is a user /
> VMM depending on the IDR5.DS bit today? The IDR5 is exposed to the user
> via hw_info AND in the uAPI documentation block we explicitly mention 
> for struct iommu_hw_info_arm_smmuv3 the following valid fields for IDR5:
>
> idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K

Probably soon we will add DS to that comment and it will be fully
backwards compatible so a new VMM following the new guidance can just
read DS.

Thus we can't have any kernel release that doesn't work with a VMM
following DS...

Jason