[PATCH 0/3] Enable quad SPI mode for SPI-NAND on IPQ RDP boards

[PATCH 0/3] Enable quad SPI mode for SPI-NAND on IPQ RDP boards

[Md Sadre Alam]

Several Qualcomm IPQ RDP platforms support quad (x4) SPI transfers
between the QPIC SPI-NAND controller and the attached SPI-NAND device.
However, the corresponding device trees do not currently describe the
bus width capabilities of the flash device, causing transfers to fall
back to the default single-bit (x1) mode.

This series enables quad SPI operation on supported IPQ reference
design platforms by adding spi-rx-bus-width and spi-tx-bus-width
properties to the SPI-NAND device nodes.

The series updates the IPQ9574, IPQ5424 and IPQ5332 based RDPs.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
Md Sadre Alam (3):
      arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND
      arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND
      arm64: dts: qcom: ipq5332-rdp-common: Enable quad SPI mode for SPI-NAND

 arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 2 ++
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts      | 2 ++
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 2 ++
 3 files changed, 6 insertions(+)
---
base-commit: 19827e7930a5511c68e12aac6e4522f3661a1709
change-id: 20260716-quad_dts-6bac0484c08c
prerequisite-change-id: 20260716-quad-ec2765317214:v1
prerequisite-patch-id: 912ede01168ddf0476ba69ab0db786186073f817
prerequisite-patch-id: cdb88acd348e7dc5136fa9b94cc06dcafb0f478d
prerequisite-patch-id: 932ca3dc3893df6de25928b24c7c24550907088d

Best regards,
-- 
Md Sadre Alam <md.alam@oss.qualcomm.com>

[PATCH 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

[Md Sadre Alam]

Set the SPI-NAND device node to use 4-bit transmit and receive bus widths.

The board supports quad SPI transfers, but the device tree currently does
not describe the wider bus. Add spi-tx-bus-width and spi-rx-bus-width so
the controller and flash can use quad mode instead of single-bit transfers.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index 62877b46f9b3..86138529ba77 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -249,6 +249,8 @@ flash@0 {
 		nand-ecc-engine = <&qpic_nand>;
 		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };
 

-- 
2.34.1

[PATCH 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

[Md Sadre Alam]

Enable quad SPI transfers for the SPI-NAND device by setting both spi-rx-
bus-width and spi-tx-bus-width to 4.

Without these properties, the device uses the default single-bit bus width.
Configure the board to use 4-bit read and write transfers so the controller
and flash can operate in quad SPI mode.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index be8657239c46..793afc3ee82e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -261,6 +261,8 @@ flash@0 {
 		nand-ecc-engine = <&qpic_nand>;
 		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };
 

-- 
2.34.1

[PATCH 3/3] arm64: dts: qcom: ipq5332-rdp-common: Enable quad SPI mode for SPI-NAND

[Md Sadre Alam]

The SPI-NAND device on the IPQ5332 RDP supports 4-bit data transfers, but
the device tree does not describe the bus width, so transfers use the
default single-bit mode.

Set spi-rx-bus-width and spi-tx-bus-width to 4 to enable quad read and
write transfers and improve SPI-NAND throughput.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
index 3bbf748f2e5c..6f5b193a204b 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
@@ -141,5 +141,7 @@ flash@0 {
 		nand-ecc-engine = <&qpic_nand>;
 		nand-ecc-strength = <4>;
 		nand-ecc-step-size = <512>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

-- 
2.34.1

Re: [PATCH 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Adding `spi-tx-bus-width = <4>` breaks SPI-NAND page writes because the underlying QPIC SPI controller driver does not support quad program opcodes, and `spi-rx-bus-width = <4>` silently fails to enable quad reads.
--

--- Patch [2]: [PATCH 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND ---
commit d94d344a7a9d7f1e09d33f7fca995cd1adf27026
Author: Md Sadre Alam <md.alam@oss.qualcomm.com>

arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

This commit configures the SPI-NAND device to use 4-bit bus widths for
both transmit and receive by adding spi-rx-bus-width and spi-tx-bus-width
properties to the device tree.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> @@ -257,6 +257,8 @@ flash@0 {
>  		nand-ecc-engine = <&qpic_nand>;
>  		nand-ecc-strength = <4>;
>  		nand-ecc-step-size = <512>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;

[Severity: High]
Does setting spi-tx-bus-width to 4 break SPI-NAND page writes on this
platform?

The SPI-NAND core parses this property and will attempt to issue quad
program opcodes during page writes. However, looking at the underlying QPIC
SPI controller driver, it appears to reject any program load opcode except
the 1-bit 0x84 opcode:

drivers/spi/spi-qpic-snand.c:qcom_spi_cmd_mapping() {
    ...
    default:
        dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
        return -EOPNOTSUPP;
}

When the core issues a quad program opcode (like 0x32), the driver will
return -EOPNOTSUPP, causing all write operations to the storage to fail. Is
the QPIC SPI driver missing support for quad page program opcodes, or should
the tx width remain at 1-bit in the device tree?

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716-quad_dts-v1-0-74d86792944a@oss.qualcomm.com?part=2

Re: [PATCH 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] The device tree changes attempt to enable Quad SPI mode, but the underlying controller driver hardcodes single-bit transfers.
--

--- Patch [1]: [PATCH 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND ---
commit fa94f9522a125598be3f36fef708de141603218d
Author: Md Sadre Alam <md.alam@oss.qualcomm.com>

arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

This commit sets the SPI-NAND device node to use 4-bit transmit and
receive bus widths to enable quad SPI transfers.

> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> index 62877b46f9b3f..86138529ba77e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> @@ -249,6 +249,8 @@ flash@0 {
>  		nand-ecc-engine = <&qpic_nand>;
>  		nand-ecc-strength = <4>;
>  		nand-ecc-step-size = <512>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;

[Severity: Medium]
This is a pre-existing issue, but does enabling the 4-bit bus width here
actually result in quad SPI transfers?

Looking at the QPIC controller driver in drivers/spi/spi-qpic-snand.c,
qcom_spi_cmd_mapping() intercepts generic SPI NAND opcodes and hardcodes
SPI_TRANSFER_MODE_x1:

drivers/spi/spi-qpic-snand.c:qcom_spi_cmd_mapping() {
        ...
	case SPINAND_READ:
		if (snandc->qspi->raw_rw) {
			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
					SPI_WP | SPI_HOLD | OP_PAGE_READ);
		} else {
			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
					SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
		}
        ...
}

It appears the driver completely ignores the bus widths negotiated by the
spi-mem framework, meaning transfers will silently remain single-bit.

Are there companion patches to the controller driver to handle the wider
bus widths, or is this device tree change ineffective on its own?

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716-quad_dts-v1-0-74d86792944a@oss.qualcomm.com?part=1

Re: [PATCH 0/3] Enable quad SPI mode for SPI-NAND on IPQ RDP boards

[Mukesh Ojha]

On Thu, Jul 16, 2026 at 11:25:11AM +0530, Md Sadre Alam wrote:
> Several Qualcomm IPQ RDP platforms support quad (x4) SPI transfers
> between the QPIC SPI-NAND controller and the attached SPI-NAND device.
> However, the corresponding device trees do not currently describe the
> bus width capabilities of the flash device, causing transfers to fall
> back to the default single-bit (x1) mode.
> 
> This series enables quad SPI operation on supported IPQ reference
> design platforms by adding spi-rx-bus-width and spi-tx-bus-width
> properties to the SPI-NAND device nodes.
> 
> The series updates the IPQ9574, IPQ5424 and IPQ5332 based RDPs.
> 
> Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
> ---
> Md Sadre Alam (3):
>       arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND
>       arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND
>       arm64: dts: qcom: ipq5332-rdp-common: Enable quad SPI mode for SPI-NAND
> 
>  arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 2 ++
>  arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts      | 2 ++
>  arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 2 ++
>  3 files changed, 6 insertions(+)
> ---
> base-commit: 19827e7930a5511c68e12aac6e4522f3661a1709
> change-id: 20260716-quad_dts-6bac0484c08c
> prerequisite-change-id: 20260716-quad-ec2765317214:v1

Above does not help.  Be explicit here in the cover letter by
providing the dependency link directly.

> prerequisite-patch-id: 912ede01168ddf0476ba69ab0db786186073f817
> prerequisite-patch-id: cdb88acd348e7dc5136fa9b94cc06dcafb0f478d
> prerequisite-patch-id: 932ca3dc3893df6de25928b24c7c24550907088d
> 
> Best regards,
> -- 
> Md Sadre Alam <md.alam@oss.qualcomm.com>
> 

-- 
-Mukesh Ojha

Re: [PATCH 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

[Konrad Dybcio]

On 7/16/26 7:55 AM, Md Sadre Alam wrote:
> Set the SPI-NAND device node to use 4-bit transmit and receive bus widths.
> 
> The board supports quad SPI transfers, but the device tree currently does
> not describe the wider bus. Add spi-tx-bus-width and spi-rx-bus-width so
> the controller and flash can use quad mode instead of single-bit transfers.
> 
> Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

[Konrad Dybcio]

On 7/16/26 7:55 AM, Md Sadre Alam wrote:
> Enable quad SPI transfers for the SPI-NAND device by setting both spi-rx-
> bus-width and spi-tx-bus-width to 4.
> 
> Without these properties, the device uses the default single-bit bus width.
> Configure the board to use 4-bit read and write transfers so the controller
> and flash can operate in quad SPI mode.
> 
> Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 3/3] arm64: dts: qcom: ipq5332-rdp-common: Enable quad SPI mode for SPI-NAND

[Konrad Dybcio]

On 7/16/26 7:55 AM, Md Sadre Alam wrote:
> The SPI-NAND device on the IPQ5332 RDP supports 4-bit data transfers, but
> the device tree does not describe the bus width, so transfers use the
> default single-bit mode.
> 
> Set spi-rx-bus-width and spi-tx-bus-width to 4 to enable quad read and
> write transfers and improve SPI-NAND throughput.
> 
> Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad