[PATCH v2 0/2] i3c: dw: Document optional core reset and drop redundant name

[PATCH v2 0/2] i3c: dw: Document optional core reset and drop redundant name

[Shubham Patil]

This series documents the optional core reset for the Synopsys
DesignWare I3C master and updates the driver to match the binding.
The DesignWare I3C master IP has a single core reset input. The
binding never documented this reset, and the driver looked it up by
the "core_rst" name even though a name is redundant for a single
reset line.

This series addresses both:
  - Patch 1 documents the optional 'resets' property in the binding.
    The reset is kept optional because the reset line is
    integration-specific.
  - Patch 2 removes the "core_rst" reset name from the driver and
    looks the reset up by passing NULL, since the name is redundant
    for a single reset.

Changes in v2:
- Updated commit description for binding patch
- Dropped reset-names from the binding
- Added driver patch to remove redundant reset name

Note:
The DesignWare I3C driver support was added by
commit 1dd728f5d4d4 ("i3c: master: Add driver for Synopsys DesignWare IP").

The original Synopsys DesignWare I3C binding was added by
commit 116e246a8bcd ("dt-binding: i3c: Document Synopsys DesignWare I3C"),
but it did not document the optional core reset.
---
Shubham Patil (2):
  dt-bindings: i3c: dw: Document missing optional core reset
  i3c: master: dw: Drop redundant core reset name

 Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
 drivers/i3c/master/dw-i3c-master.c                            | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)


base-commit: a13c140cc289c0b7b3770bce5b3ad42ab35074aa
-- 
2.34.1


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[PATCH v2 0/2] i3c: dw: Document optional core reset and drop redundant name

[Shubham Patil]

This series documents the optional core reset for the Synopsys
DesignWare I3C master and updates the driver to match the binding.
The DesignWare I3C master IP has a single core reset input. The
binding never documented this reset, and the driver looked it up by
the "core_rst" name even though a name is redundant for a single
reset line.

This series addresses both:
  - Patch 1 documents the optional 'resets' property in the binding.
    The reset is kept optional because the reset line is
    integration-specific.
  - Patch 2 removes the "core_rst" reset name from the driver and
    looks the reset up by passing NULL, since the name is redundant
    for a single reset.

Changes in v2:
- Updated commit description for binding patch
- Dropped reset-names from the binding
- Added driver patch to remove redundant reset name

Note:
The DesignWare I3C driver support was added by
commit 1dd728f5d4d4 ("i3c: master: Add driver for Synopsys DesignWare IP").

The original Synopsys DesignWare I3C binding was added by
commit 116e246a8bcd ("dt-binding: i3c: Document Synopsys DesignWare I3C"),
but it did not document the optional core reset.
---
Shubham Patil (2):
  dt-bindings: i3c: dw: Document missing optional core reset
  i3c: master: dw: Drop redundant core reset name

 Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
 drivers/i3c/master/dw-i3c-master.c                            | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)


base-commit: a13c140cc289c0b7b3770bce5b3ad42ab35074aa
-- 
2.34.1

[PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[Shubham Patil]

The DesignWare I3C master IP supports a core reset input, but the
binding is missing the corresponding reset description.

Document the optional reset property. Keep it optional because the
reset line is integration-specific.

Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
---
Changes in v2:
- Updated commit description
- Dropped reset-name from the binding
---
 Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index e803457d3f55..dc7ee38001d6 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -38,6 +38,9 @@ properties:
   interrupts:
     maxItems: 1
 
+  resets:
+    maxItems: 1
+
   power-domains:
     maxItems: 1
 
-- 
2.34.1


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[PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[Shubham Patil]

The DesignWare I3C master IP supports a core reset input, but the
binding is missing the corresponding reset description.

Document the optional reset property. Keep it optional because the
reset line is integration-specific.

Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
---
Changes in v2:
- Updated commit description
- Dropped reset-name from the binding
---
 Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index e803457d3f55..dc7ee38001d6 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -38,6 +38,9 @@ properties:
   interrupts:
     maxItems: 1
 
+  resets:
+    maxItems: 1
+
   power-domains:
     maxItems: 1
 
-- 
2.34.1

Re: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[Pandey, Radhey Shyam]

On 7/20/2026 1:05 PM, Shubham Patil wrote:
> The DesignWare I3C master IP supports a core reset input, but the
> binding is missing the corresponding reset description.
> 
> Document the optional reset property. Keep it optional because the
> reset line is integration-specific.
> 
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!
> ---
> Changes in v2:
> - Updated commit description
> - Dropped reset-name from the binding
> ---
>   Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index e803457d3f55..dc7ee38001d6 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -38,6 +38,9 @@ properties:
>     interrupts:
>       maxItems: 1
>   
> +  resets:
> +    maxItems: 1
> +
>     power-domains:
>       maxItems: 1
>   

Re: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[Pandey, Radhey Shyam]

On 7/20/2026 1:05 PM, Shubham Patil wrote:
> The DesignWare I3C master IP supports a core reset input, but the
> binding is missing the corresponding reset description.
> 
> Document the optional reset property. Keep it optional because the
> reset line is integration-specific.
> 
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!
> ---
> Changes in v2:
> - Updated commit description
> - Dropped reset-name from the binding
> ---
>   Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index e803457d3f55..dc7ee38001d6 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -38,6 +38,9 @@ properties:
>     interrupts:
>       maxItems: 1
>   
> +  resets:
> +    maxItems: 1
> +
>     power-domains:
>       maxItems: 1
>   


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Re: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The binding schema adds the `resets` property but intentionally omits `reset-names`. The driver strictly requires `reset-names = "core_rst"` to find the reset control, causing it to silently ignore the reset.
--

--- Patch [1]: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset ---
commit 673b06088a9b59875d717db2c9afb56295ac87a9
Author: Shubham Patil <shubhamsanjay.patil@amd.com>

dt-bindings: i3c: dw: Document missing optional core reset

This commit documents an optional core reset property for the DesignWare I3C
master IP. It adds the resets property with a maxItems of 1 to the schema
but explicitly drops the reset-name property.

> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index e803457d3f554..dc7ee38001d6d 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -38,6 +38,9 @@ properties:
>    interrupts:
>      maxItems: 1
>  
> +  resets:
> +    maxItems: 1
> +

[Severity: High]
Since this schema intentionally omits reset-names, device trees cannot
provide it without breaking schema validation.

However, doesn't the driver explicitly rely on reset-names to find this
reset control?

Looking at dw_i3c_common_probe() in drivers/i3c/master/dw-i3c-master.c:

	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(
					&pdev->dev, "core_rst");

Because this searches for the "core_rst" string in the reset-names
property, won't it fail to find the reset and silently return NULL
without the property being defined in the device tree?

This would turn all subsequent reset operations into no-ops. Should
reset-names be added back to the binding to match the driver's
expectations?

>    power-domains:
>      maxItems: 1
>

-- 
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Re: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The binding schema adds the `resets` property but intentionally omits `reset-names`. The driver strictly requires `reset-names = "core_rst"` to find the reset control, causing it to silently ignore the reset.
--

--- Patch [1]: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset ---
commit 673b06088a9b59875d717db2c9afb56295ac87a9
Author: Shubham Patil <shubhamsanjay.patil@amd.com>

dt-bindings: i3c: dw: Document missing optional core reset

This commit documents an optional core reset property for the DesignWare I3C
master IP. It adds the resets property with a maxItems of 1 to the schema
but explicitly drops the reset-name property.

> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index e803457d3f554..dc7ee38001d6d 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -38,6 +38,9 @@ properties:
>    interrupts:
>      maxItems: 1
>  
> +  resets:
> +    maxItems: 1
> +

[Severity: High]
Since this schema intentionally omits reset-names, device trees cannot
provide it without breaking schema validation.

However, doesn't the driver explicitly rely on reset-names to find this
reset control?

Looking at dw_i3c_common_probe() in drivers/i3c/master/dw-i3c-master.c:

	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(
					&pdev->dev, "core_rst");

Because this searches for the "core_rst" string in the reset-names
property, won't it fail to find the reset and silently return NULL
without the property being defined in the device tree?

This would turn all subsequent reset operations into no-ops. Should
reset-names be added back to the binding to match the driver's
expectations?

>    power-domains:
>      maxItems: 1
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260720073510.1869623-1-shubhamsanjay.patil@amd.com?part=1

Re: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[Frank Li]

On Mon, Jul 20, 2026 at 01:05:09PM +0530, Shubham Patil wrote:
> The DesignWare I3C master IP supports a core reset input, but the
> binding is missing the corresponding reset description.
>
> Document the optional reset property. Keep it optional because the
> reset line is integration-specific.
>
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> Changes in v2:
> - Updated commit description
> - Dropped reset-name from the binding
> ---
>  Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index e803457d3f55..dc7ee38001d6 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -38,6 +38,9 @@ properties:
>    interrupts:
>      maxItems: 1
>
> +  resets:
> +    maxItems: 1
> +
>    power-domains:
>      maxItems: 1
>
> --
> 2.34.1
>

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Re: [PATCH v2 1/2] dt-bindings: i3c: dw: Document missing optional core reset

[Frank Li]

On Mon, Jul 20, 2026 at 01:05:09PM +0530, Shubham Patil wrote:
> The DesignWare I3C master IP supports a core reset input, but the
> binding is missing the corresponding reset description.
>
> Document the optional reset property. Keep it optional because the
> reset line is integration-specific.
>
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> Changes in v2:
> - Updated commit description
> - Dropped reset-name from the binding
> ---
>  Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index e803457d3f55..dc7ee38001d6 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -38,6 +38,9 @@ properties:
>    interrupts:
>      maxItems: 1
>
> +  resets:
> +    maxItems: 1
> +
>    power-domains:
>      maxItems: 1
>
> --
> 2.34.1
>

[PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[Shubham Patil]

The DesignWare I3C master has a single reset line, so a dedicated
reset name is redundant. Look up the reset by index by passing NULL
instead of the "core_rst" name.

Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
---
 drivers/i3c/master/dw-i3c-master.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 2f8c0c4683e0..488fb455d3cc 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
 		return PTR_ERR(master->pclk);
 
 	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
-										"core_rst");
+										NULL);
 	if (IS_ERR(master->core_rst))
 		return PTR_ERR(master->core_rst);
 
-- 
2.34.1


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[PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[Shubham Patil]

The DesignWare I3C master has a single reset line, so a dedicated
reset name is redundant. Look up the reset by index by passing NULL
instead of the "core_rst" name.

Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
---
 drivers/i3c/master/dw-i3c-master.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 2f8c0c4683e0..488fb455d3cc 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
 		return PTR_ERR(master->pclk);
 
 	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
-										"core_rst");
+										NULL);
 	if (IS_ERR(master->core_rst))
 		return PTR_ERR(master->core_rst);
 
-- 
2.34.1

Re: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[Pandey, Radhey Shyam]

On 7/20/2026 1:05 PM, Shubham Patil wrote:
> The DesignWare I3C master has a single reset line, so a dedicated
> reset name is redundant. Look up the reset by index by passing NULL
> instead of the "core_rst" name.
> 
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!

> ---
>   drivers/i3c/master/dw-i3c-master.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 2f8c0c4683e0..488fb455d3cc 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>   		return PTR_ERR(master->pclk);
>   
>   	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> -										"core_rst");
> +										NULL);
>   	if (IS_ERR(master->core_rst))
>   		return PTR_ERR(master->core_rst);
>   

Re: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[Pandey, Radhey Shyam]

On 7/20/2026 1:05 PM, Shubham Patil wrote:
> The DesignWare I3C master has a single reset line, so a dedicated
> reset name is redundant. Look up the reset by index by passing NULL
> instead of the "core_rst" name.
> 
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!

> ---
>   drivers/i3c/master/dw-i3c-master.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 2f8c0c4683e0..488fb455d3cc 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>   		return PTR_ERR(master->pclk);
>   
>   	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> -										"core_rst");
> +										NULL);
>   	if (IS_ERR(master->core_rst))
>   		return PTR_ERR(master->core_rst);
>   


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Re: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] Missing device wakeup in the remove path causes unbalanced devres cleanup (double clock disable and double reset assert) if the device is in runtime suspend.
--

--- Patch [2]: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name ---
commit 6e023481fe0a3988544e2173709b9f994efee394
Author: Shubham Patil <shubhamsanjay.patil@amd.com>

i3c: master: dw: Drop redundant core reset name

The DesignWare I3C master has a single reset line, so a dedicated
reset name is redundant. Look up the reset by index by passing NULL
instead of the "core_rst" name.

> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 2f8c0c4683e06..488fb455d3cc8 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>  		return PTR_ERR(master->pclk);
>  
>  	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> -										"core_rst");
> +										NULL);

[Severity: Medium]
This is a pre-existing issue, but touching this devm allocation raises a
question about how devres cleans up during driver unbind.

Since devm_reset_control_get_optional_exclusive_deasserted() and the earlier
devm_clk_get_enabled() register devres actions to assert resets and disable
clocks, does dw_i3c_common_remove() need to wake the device before teardown?

If the device is runtime suspended during driver unbind,
dw_i3c_master_runtime_suspend() has already disabled clocks and asserted the
reset. Because dw_i3c_common_remove() does not call pm_runtime_get_sync() to
resume the device:

void dw_i3c_common_remove(struct dw_i3c_master *master)
{
	i3c_master_unregister(&master->base);

	/* Balance pm_runtime_get_noresume() from probe() */
	if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
		pm_runtime_put_noidle(master->dev);

	pm_runtime_disable(master->dev);
	pm_runtime_set_suspended(master->dev);
	pm_runtime_dont_use_autosuspend(master->dev);
}

The automatic devres cleanup will attempt to disable already-disabled clocks
and assert an already-asserted reset, which could trigger a noisy WARN from
the Common Clock Framework.

Could this double-cleanup be avoided by resuming the device before disabling
runtime PM in dw_i3c_common_remove()?

>  	if (IS_ERR(master->core_rst))
>  		return PTR_ERR(master->core_rst);
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260720073510.1869623-1-shubhamsanjay.patil@amd.com?part=2

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Re: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] Missing device wakeup in the remove path causes unbalanced devres cleanup (double clock disable and double reset assert) if the device is in runtime suspend.
--

--- Patch [2]: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name ---
commit 6e023481fe0a3988544e2173709b9f994efee394
Author: Shubham Patil <shubhamsanjay.patil@amd.com>

i3c: master: dw: Drop redundant core reset name

The DesignWare I3C master has a single reset line, so a dedicated
reset name is redundant. Look up the reset by index by passing NULL
instead of the "core_rst" name.

> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 2f8c0c4683e06..488fb455d3cc8 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>  		return PTR_ERR(master->pclk);
>  
>  	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> -										"core_rst");
> +										NULL);

[Severity: Medium]
This is a pre-existing issue, but touching this devm allocation raises a
question about how devres cleans up during driver unbind.

Since devm_reset_control_get_optional_exclusive_deasserted() and the earlier
devm_clk_get_enabled() register devres actions to assert resets and disable
clocks, does dw_i3c_common_remove() need to wake the device before teardown?

If the device is runtime suspended during driver unbind,
dw_i3c_master_runtime_suspend() has already disabled clocks and asserted the
reset. Because dw_i3c_common_remove() does not call pm_runtime_get_sync() to
resume the device:

void dw_i3c_common_remove(struct dw_i3c_master *master)
{
	i3c_master_unregister(&master->base);

	/* Balance pm_runtime_get_noresume() from probe() */
	if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
		pm_runtime_put_noidle(master->dev);

	pm_runtime_disable(master->dev);
	pm_runtime_set_suspended(master->dev);
	pm_runtime_dont_use_autosuspend(master->dev);
}

The automatic devres cleanup will attempt to disable already-disabled clocks
and assert an already-asserted reset, which could trigger a noisy WARN from
the Common Clock Framework.

Could this double-cleanup be avoided by resuming the device before disabling
runtime PM in dw_i3c_common_remove()?

>  	if (IS_ERR(master->core_rst))
>  		return PTR_ERR(master->core_rst);
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260720073510.1869623-1-shubhamsanjay.patil@amd.com?part=2

Re: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[Frank Li]

On Mon, Jul 20, 2026 at 01:05:10PM +0530, Shubham Patil wrote:
> The DesignWare I3C master has a single reset line, so a dedicated
> reset name is redundant. Look up the reset by index by passing NULL
> instead of the "core_rst" name.
>
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/i3c/master/dw-i3c-master.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 2f8c0c4683e0..488fb455d3cc 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>  		return PTR_ERR(master->pclk);
>
>  	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> -										"core_rst");
> +										NULL);
>  	if (IS_ERR(master->core_rst))
>  		return PTR_ERR(master->core_rst);
>
> --
> 2.34.1
>

Re: [PATCH v2 2/2] i3c: master: dw: Drop redundant core reset name

[Frank Li]

On Mon, Jul 20, 2026 at 01:05:10PM +0530, Shubham Patil wrote:
> The DesignWare I3C master has a single reset line, so a dedicated
> reset name is redundant. Look up the reset by index by passing NULL
> instead of the "core_rst" name.
>
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/i3c/master/dw-i3c-master.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 2f8c0c4683e0..488fb455d3cc 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1584,7 +1584,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
>  		return PTR_ERR(master->pclk);
>
>  	master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> -										"core_rst");
> +										NULL);
>  	if (IS_ERR(master->core_rst))
>  		return PTR_ERR(master->core_rst);
>
> --
> 2.34.1
>

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