* [PATCH RESEND 0/2] memory: mtk-smi: add MT8189 SMI support
@ 2026-07-22 9:21 ` Congcong Yao
0 siblings, 0 replies; 8+ messages in thread
From: Congcong Yao via B4 Relay @ 2026-07-22 9:21 UTC (permalink / raw)
To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, Rob Herring, Conor Dooley
Cc: linux-mediatek, linux-kernel, linux-arm-kernel, devicetree,
Congcong Yao
Based on tag: next-20260629, linux-next/master
This patchset adds MT8189 SMI support.
The series updates the MediaTek SMI bindings for MT8189 and adds the
corresponding SMI common and larb support in the mtk-smi driver.
This is a resend of v3. No code changes.
Changes in v3:
- Change the minimum clock number of smi-sub-common to 3.
- Link to v2:
https://lore.kernel.org/linux-mediatek/20260427070444.20247-1-zhengnan.chen@mediatek.com/
Signed-off-by: Congcong Yao <congcong.yao@mediatek.com>
---
Congcong Yao (2):
memory: mtk-smi: Add mt8189 support
dt-bindings: memory-controllers: mtk-smi: Add support for mt8189
.../memory-controllers/mediatek,smi-common.yaml | 18 +++++++++
.../memory-controllers/mediatek,smi-larb.yaml | 3 ++
drivers/memory/mtk-smi.c | 44 ++++++++++++++++++++++
3 files changed, 65 insertions(+)
---
base-commit: 290aaf24a551d5a0dce037e3fab30820f9113a10
change-id: 20260722-8189-smi-support-e22d97ee071b
Best regards,
--
Congcong Yao <congcong.yao@mediatek.com>
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH RESEND 0/2] memory: mtk-smi: add MT8189 SMI support @ 2026-07-22 9:21 ` Congcong Yao 0 siblings, 0 replies; 8+ messages in thread From: Congcong Yao @ 2026-07-22 9:21 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring, Conor Dooley Cc: linux-mediatek, linux-kernel, linux-arm-kernel, devicetree, Congcong Yao Based on tag: next-20260629, linux-next/master This patchset adds MT8189 SMI support. The series updates the MediaTek SMI bindings for MT8189 and adds the corresponding SMI common and larb support in the mtk-smi driver. This is a resend of v3. No code changes. Changes in v3: - Change the minimum clock number of smi-sub-common to 3. - Link to v2: https://lore.kernel.org/linux-mediatek/20260427070444.20247-1-zhengnan.chen@mediatek.com/ Signed-off-by: Congcong Yao <congcong.yao@mediatek.com> --- Congcong Yao (2): memory: mtk-smi: Add mt8189 support dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 .../memory-controllers/mediatek,smi-common.yaml | 18 +++++++++ .../memory-controllers/mediatek,smi-larb.yaml | 3 ++ drivers/memory/mtk-smi.c | 44 ++++++++++++++++++++++ 3 files changed, 65 insertions(+) --- base-commit: 290aaf24a551d5a0dce037e3fab30820f9113a10 change-id: 20260722-8189-smi-support-e22d97ee071b Best regards, -- Congcong Yao <congcong.yao@mediatek.com> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH RESEND 1/2] memory: mtk-smi: Add mt8189 support 2026-07-22 9:21 ` Congcong Yao @ 2026-07-22 9:21 ` Congcong Yao -1 siblings, 0 replies; 8+ messages in thread From: Congcong Yao via B4 Relay @ 2026-07-22 9:21 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring, Conor Dooley Cc: linux-mediatek, linux-kernel, linux-arm-kernel, devicetree, Congcong Yao From: Congcong Yao <congcong.yao@mediatek.com> Add the necessary platform data and ostdl setting to enable support for mt8189 smi. Signed-off-by: Congcong Yao <congcong.yao@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Yong Wu <yong.wu@mediatek.com> --- drivers/memory/mtk-smi.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index aaeba8ab211e..f2d5462af681 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -401,6 +401,30 @@ static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = { [25] = {0x01}, }; +static const u8 mtk_smi_larb_mt8189_ostd[][SMI_LARB_PORT_NR_MAX] = { + [0] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, + [1] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, + [2] = {0x7, 0x7, 0x4, 0x4, 0x0, 0x0, 0x2, 0x2, 0x7, 0x7, 0x0,}, + [4] = {0x2F, 0x1E, 0x9, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x5, 0x1, 0x17,}, + [7] = {0x20, 0x2, 0x1, 0x1, 0x1, 0x4, 0x2, 0x1, 0x1, 0x2, 0x3, 0x2, + 0xA, 0xF, 0x4, 0x6, 0x5, 0x1,}, + [9] = {0x6, 0x3, 0xC, 0x6, 0x1, 0x4, 0x3, 0x1, 0x2, 0x4, 0x5, 0x2, + 0x4, 0x2, 0x3, 0xB, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1,}, + [11] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1, 0x1, 0xB, 0x1, 0x4, 0x6, 0x5, 0x6, 0x1, 0x5, 0x2, + 0x9, 0x5,}, + [13] = {0x2, 0x8, 0x8, 0x8, 0x4, 0x4, 0x4, 0x4, 0x4, 0xE, 0x4, 0x1, + 0x6, 0x6, 0x2,}, + [14] = {0x1, 0x1, 0x1, 0x20, 0xE, 0x4, 0x8, 0x8, 0x6, 0x4,}, + [16] = {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [17] = {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [19] = {0x2, 0x1, 0x3, 0x1,}, + [20] = {0x7, 0x7, 0x3, 0x3, 0x1, 0x1,}, +}; + static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] = { [0] = {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,}, [1] = {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,}, @@ -533,6 +557,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = { .ostd = mtk_smi_larb_mt8188_ostd, }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8189 = { + .config_port = mtk_smi_larb_config_port_gen2_general, + .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | + MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, + .ostd = mtk_smi_larb_mt8189_ostd, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { .config_port = mtk_smi_larb_config_port_gen2_general, .ostd = mtk_smi_larb_mt8192_ostd, @@ -556,6 +587,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188}, + {.compatible = "mediatek,mt8189-smi-larb", .data = &mtk_smi_larb_mt8189}, {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, {} @@ -808,6 +840,16 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = { .init = mtk_smi_common_mt8195_init, }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8189 = { + .type = MTK_SMI_GEN2, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | + F_MMU1_LARB(7), +}; + +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8189 = { + .type = MTK_SMI_GEN2_SUB_COMM, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { .type = MTK_SMI_GEN2, .has_gals = true, @@ -852,6 +894,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo}, {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp}, + {.compatible = "mediatek,mt8189-smi-common", .data = &mtk_smi_common_mt8189}, + {.compatible = "mediatek,mt8189-smi-sub-common", .data = &mtk_smi_sub_common_mt8189}, {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH RESEND 1/2] memory: mtk-smi: Add mt8189 support @ 2026-07-22 9:21 ` Congcong Yao 0 siblings, 0 replies; 8+ messages in thread From: Congcong Yao @ 2026-07-22 9:21 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring, Conor Dooley Cc: linux-mediatek, linux-kernel, linux-arm-kernel, devicetree, Congcong Yao Add the necessary platform data and ostdl setting to enable support for mt8189 smi. Signed-off-by: Congcong Yao <congcong.yao@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Yong Wu <yong.wu@mediatek.com> --- drivers/memory/mtk-smi.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index aaeba8ab211e..f2d5462af681 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -401,6 +401,30 @@ static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = { [25] = {0x01}, }; +static const u8 mtk_smi_larb_mt8189_ostd[][SMI_LARB_PORT_NR_MAX] = { + [0] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, + [1] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, + [2] = {0x7, 0x7, 0x4, 0x4, 0x0, 0x0, 0x2, 0x2, 0x7, 0x7, 0x0,}, + [4] = {0x2F, 0x1E, 0x9, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x5, 0x1, 0x17,}, + [7] = {0x20, 0x2, 0x1, 0x1, 0x1, 0x4, 0x2, 0x1, 0x1, 0x2, 0x3, 0x2, + 0xA, 0xF, 0x4, 0x6, 0x5, 0x1,}, + [9] = {0x6, 0x3, 0xC, 0x6, 0x1, 0x4, 0x3, 0x1, 0x2, 0x4, 0x5, 0x2, + 0x4, 0x2, 0x3, 0xB, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1,}, + [11] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1, 0x1, 0xB, 0x1, 0x4, 0x6, 0x5, 0x6, 0x1, 0x5, 0x2, + 0x9, 0x5,}, + [13] = {0x2, 0x8, 0x8, 0x8, 0x4, 0x4, 0x4, 0x4, 0x4, 0xE, 0x4, 0x1, + 0x6, 0x6, 0x2,}, + [14] = {0x1, 0x1, 0x1, 0x20, 0xE, 0x4, 0x8, 0x8, 0x6, 0x4,}, + [16] = {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [17] = {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [19] = {0x2, 0x1, 0x3, 0x1,}, + [20] = {0x7, 0x7, 0x3, 0x3, 0x1, 0x1,}, +}; + static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] = { [0] = {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,}, [1] = {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,}, @@ -533,6 +557,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = { .ostd = mtk_smi_larb_mt8188_ostd, }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8189 = { + .config_port = mtk_smi_larb_config_port_gen2_general, + .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | + MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, + .ostd = mtk_smi_larb_mt8189_ostd, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { .config_port = mtk_smi_larb_config_port_gen2_general, .ostd = mtk_smi_larb_mt8192_ostd, @@ -556,6 +587,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188}, + {.compatible = "mediatek,mt8189-smi-larb", .data = &mtk_smi_larb_mt8189}, {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, {} @@ -808,6 +840,16 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = { .init = mtk_smi_common_mt8195_init, }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8189 = { + .type = MTK_SMI_GEN2, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | + F_MMU1_LARB(7), +}; + +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8189 = { + .type = MTK_SMI_GEN2_SUB_COMM, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { .type = MTK_SMI_GEN2, .has_gals = true, @@ -852,6 +894,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo}, {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp}, + {.compatible = "mediatek,mt8189-smi-common", .data = &mtk_smi_common_mt8189}, + {.compatible = "mediatek,mt8189-smi-sub-common", .data = &mtk_smi_sub_common_mt8189}, {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH RESEND 1/2] memory: mtk-smi: Add mt8189 support 2026-07-22 9:21 ` Congcong Yao (?) @ 2026-07-22 9:40 ` sashiko-bot -1 siblings, 0 replies; 8+ messages in thread From: sashiko-bot @ 2026-07-22 9:40 UTC (permalink / raw) To: Congcong Yao; +Cc: robh, conor+dt, devicetree Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] The newly added OSTD array for MT8189 contains 0x0 values in the middle of port configuration lists, which will cause the initialization loop to prematurely terminate and skip remaining ports. - [High] The `mtk_smi_larb_mt8189_ostd` array is incorrectly indexed using physical LARB IDs instead of the logical `larbid`s, leading to uninitialized (zero) configuration values being used for sparse LARBs. -- --- Patch [1]: [PATCH RESEND 1/2] memory: mtk-smi: Add mt8189 support --- commit a0aeb95996d513c82894f215895c9e39ee05a1de Author: Congcong Yao <congcong.yao@mediatek.com> memory: mtk-smi: Add mt8189 support Add the necessary platform data and ostdl setting to enable support for mt8189 smi. > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index aaeba8ab211e9..f2d5462af6817 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -401,6 +401,30 @@ static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = { > [25] = {0x01}, > }; > > +static const u8 mtk_smi_larb_mt8189_ostd[][SMI_LARB_PORT_NR_MAX] = { > + [0] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, > + [1] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, > + [2] = {0x7, 0x7, 0x4, 0x4, 0x0, 0x0, 0x2, 0x2, 0x7, 0x7, 0x0,}, [Severity: High] Does this explicit 0x0 value cause the initialization loop to prematurely terminate? During MT8189 SMI LARB initialization, mtk_smi_larb_config_port_gen2_general() iterates over the OSTD configurations. The loop uses !!larbostd[i] as a termination condition: for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) { ... } Because mtk_smi_larb_mt8189_ostd[2] explicitly specifies 0x0 for ports 4 and 5, the loop will break at port 4, completely skipping the configuration of ports 6 through 9. > + [4] = {0x2F, 0x1E, 0x9, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x5, 0x1, 0x17,}, [Severity: High] Are these indices using physical LARB IDs instead of logical contiguous IDs? The SMI device tree bindings map sparse physical LARBs to contiguous logical IDs. The SMI driver populates larb->larbid directly from this logical ID via the mediatek,larb-id DT property. If this array uses physical IDs (e.g., [4], [7], [20]), then when probing a sparse LARB like LARB 4, the driver accesses larb_gen->ostd[3] (its logical ID), which is empty. This would lead to uninitialized zero configuration values being used for all sparse LARBs. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260722-8189-smi-support-v1-0-b528a4fd878c@mediatek.com?part=1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH RESEND 2/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 2026-07-22 9:21 ` Congcong Yao @ 2026-07-22 9:21 ` Congcong Yao -1 siblings, 0 replies; 8+ messages in thread From: Congcong Yao via B4 Relay @ 2026-07-22 9:21 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring, Conor Dooley Cc: linux-mediatek, linux-kernel, linux-arm-kernel, devicetree, Congcong Yao From: Congcong Yao <congcong.yao@mediatek.com> Add smi larb, common and sub-commom binding description for mt8189. About what smi-sub-common is, please check the below diagram, we add it in mediatek,smi-common.yaml file. Signed-off-by: Congcong Yao <congcong.yao@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../memory-controllers/mediatek,smi-common.yaml | 18 ++++++++++++++++++ .../bindings/memory-controllers/mediatek,smi-larb.yaml | 3 +++ 2 files changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 0762e0ff66ef..4e1deeff92b1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -25,6 +25,21 @@ description: | SMI generation 1 to transform the smi clock into emi clock domain, but that is not needed for SMI generation 2. + The smi-common connects with smi-larb and IOMMU. The maximum inputs number of + a smi-common is 8. In SMI generation 2, the engines number may be over 8. + In this case, we use a smi-sub-common to merge some larbs. + The block diagram something is like: + + IOMMU + | | + smi-common + --------------------------- + | | ... + larb0 sub-common ... <-max number is 8 + ---------------- + | | ... + larb1 larbX ... <-max number is 8 + properties: compatible: oneOf: @@ -40,6 +55,8 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8189-smi-common + - mediatek,mt8189-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -108,6 +125,7 @@ allOf: compatible: contains: enum: + - mediatek,mt8189-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2e7fac4b5094..9a5dafd7c07e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb @@ -85,6 +86,7 @@ allOf: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8195-smi-larb then: @@ -119,6 +121,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH RESEND 2/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 @ 2026-07-22 9:21 ` Congcong Yao 0 siblings, 0 replies; 8+ messages in thread From: Congcong Yao @ 2026-07-22 9:21 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring, Conor Dooley Cc: linux-mediatek, linux-kernel, linux-arm-kernel, devicetree, Congcong Yao Add smi larb, common and sub-commom binding description for mt8189. About what smi-sub-common is, please check the below diagram, we add it in mediatek,smi-common.yaml file. Signed-off-by: Congcong Yao <congcong.yao@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../memory-controllers/mediatek,smi-common.yaml | 18 ++++++++++++++++++ .../bindings/memory-controllers/mediatek,smi-larb.yaml | 3 +++ 2 files changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 0762e0ff66ef..4e1deeff92b1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -25,6 +25,21 @@ description: | SMI generation 1 to transform the smi clock into emi clock domain, but that is not needed for SMI generation 2. + The smi-common connects with smi-larb and IOMMU. The maximum inputs number of + a smi-common is 8. In SMI generation 2, the engines number may be over 8. + In this case, we use a smi-sub-common to merge some larbs. + The block diagram something is like: + + IOMMU + | | + smi-common + --------------------------- + | | ... + larb0 sub-common ... <-max number is 8 + ---------------- + | | ... + larb1 larbX ... <-max number is 8 + properties: compatible: oneOf: @@ -40,6 +55,8 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8189-smi-common + - mediatek,mt8189-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -108,6 +125,7 @@ allOf: compatible: contains: enum: + - mediatek,mt8189-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2e7fac4b5094..9a5dafd7c07e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb @@ -85,6 +86,7 @@ allOf: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8195-smi-larb then: @@ -119,6 +121,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH RESEND 2/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 2026-07-22 9:21 ` Congcong Yao (?) @ 2026-07-22 9:34 ` sashiko-bot -1 siblings, 0 replies; 8+ messages in thread From: sashiko-bot @ 2026-07-22 9:34 UTC (permalink / raw) To: Congcong Yao; +Cc: robh, conor+dt, devicetree Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] Mismatch between device tree binding and driver regarding the number of required clocks for `mediatek,mt8189-smi-sub-common`. - [Low] The new compatible string `mediatek,mt8189-smi-common` is omitted from the device tree binding conditional blocks, bypassing clock validation. -- --- Patch [2]: [PATCH RESEND 2/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 --- commit cc036d50e071efdc0f20a8e8886395bb02c7e74e Author: Congcong Yao <congcong.yao@mediatek.com> dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 This commit adds device tree binding descriptions for the SMI larb, common, and sub-common hardware components on MediaTek mt8189. > diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > index 0762e0ff66ef0..4e1deeff92b14 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml [ ... ] > @@ -40,6 +55,8 @@ properties: > - mediatek,mt8186-smi-common > - mediatek,mt8188-smi-common-vdo > - mediatek,mt8188-smi-common-vpp > + - mediatek,mt8189-smi-common [Severity: Low] Should mediatek,mt8189-smi-common be added to the conditional block for gen2 hardware that lacks GALS support? Looking at the rest of the binding, there is an allOf conditional block that enforces a strict 2-clock constraint for compatible strings without GALS: - if: # for gen2 HW that don't have gals properties: compatible: enum: - mediatek,mt2712-smi-common - mediatek,mt6795-smi-common - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common then: properties: clocks: minItems: 2 maxItems: 2 Since the driver platform data for mt8189-smi-common lacks GALS support, omitting it from this conditional block bypasses the strict clock validation. > + - mediatek,mt8189-smi-sub-common > - mediatek,mt8192-smi-common [ ... ] > @@ -108,6 +125,7 @@ allOf: > compatible: > contains: > enum: > + - mediatek,mt8189-smi-sub-common [Severity: Medium] Is there a mismatch between this binding and the driver platform data regarding the number of required clocks? This schema requires 3 clocks (apb, smi, gals0) for the mediatek,mt8189-smi-sub-common hardware in this block: - if: # only for sub common properties: compatible: contains: enum: - mediatek,mt8189-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: - mediatek,smi properties: clocks: minItems: 3 maxItems: 3 However, the corresponding driver platform data in drivers/memory/mtk-smi.c omits the has_gals flag: static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8189 = { .type = MTK_SMI_GEN2_SUB_COMM, }; Because has_gals is false, the driver will only configure and enable 2 clocks. Does the hardware actually require gals0 to be configured, or is the schema overly restrictive by enforcing 3 clocks? > - mediatek,mt8195-smi-sub-common > then: > required: -- Sashiko AI review · https://sashiko.dev/#/patchset/20260722-8189-smi-support-v1-0-b528a4fd878c@mediatek.com?part=2 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-07-22 9:40 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-22 9:21 [PATCH RESEND 0/2] memory: mtk-smi: add MT8189 SMI support Congcong Yao via B4 Relay 2026-07-22 9:21 ` Congcong Yao 2026-07-22 9:21 ` [PATCH RESEND 1/2] memory: mtk-smi: Add mt8189 support Congcong Yao via B4 Relay 2026-07-22 9:21 ` Congcong Yao 2026-07-22 9:40 ` sashiko-bot 2026-07-22 9:21 ` [PATCH RESEND 2/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189 Congcong Yao via B4 Relay 2026-07-22 9:21 ` Congcong Yao 2026-07-22 9:34 ` sashiko-bot
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