[PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[Fabio Estevam via U-Boot]

From: Fabio Estevam <festevam@nabladev.com>

Add the JEDEC ID for the XMC XM25QH128C SPI NOR flash.

This is a 128Mbit device using 64KiB sectors and supporting 4KiB
erase, dual read and quad read, matching the other XM25QH128 variants.

Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
Changes since v3:
- None.

 drivers/mtd/spi/spi-nor-ids.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 31a2ba49a87c..90aa1025176c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -673,6 +673,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-- 
2.43.0

[PATCH v4 2/4] rockchip: rk3399: Remove ROC-PC regulator overrides

[Fabio Estevam via U-Boot]

From: Fabio Estevam <festevam@nabladev.com>

The upstream devicetree already describes dc_12v as the output of the
MP8859 regulator and drives the USB hub reset through the vcc5v0_host
regulator pinctrl state.

Remove the legacy fixed-regulator overrides and rely on the upstream
regulator descriptions.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Changes since v3:
- None. Only added Quentin's Reviewed-by tag.

 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index 883d399a06a3..a85e9549c83e 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -10,30 +10,6 @@
 	config {
 		sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
 	};
-
-	vcc_hub_en: vcc_hub_en-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&hub_rst>;
-		regulator-name = "vcc_hub_en";
-		regulator-always-on;
-	};
-};
-
-/*
- * should be placed inside mp8859, but not until mp8859 has
- * its own dt-binding.
- */
-&dc_12v {
-	compatible = "regulator-fixed";
-	regulator-name = "dc_12v";
-	regulator-always-on;
-	regulator-boot-on;
-	regulator-min-microvolt = <12000000>;
-	regulator-max-microvolt = <12000000>;
-	vin-supply = <&vcc_vbus_typec0>;
 };
 
 &gpio4 {
-- 
2.43.0

[PATCH v4 3/4] rockchip: rk3399: Add ROC-PC-PLUS board detection

[Fabio Estevam via U-Boot]

From: Fabio Estevam <festevam@nabladev.com>

The ROC-RK3399-PC has an MP8859 regulator on I2C7 at address 0x66,
while the ROC-RK3399-PC-PLUS does not. Probe for the regulator in SPL
and use the result to select the matching devicetree from the U-Boot
FIT. Fall back to the original board if the I2C bus cannot be probed.

Build both devicetrees from the existing roc-pc-rk3399_defconfig and
enable the XMC SPI NOR driver used by the Plus variant. Set fdtfile
from the selected U-Boot devicetree so the matching Linux devicetree
is used as well.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
Changes since v3:
- Explicitly sets fdtfile for both PC and PC-PLUS.

 arch/arm/dts/rk3399-roc-pc-plus-u-boot.dtsi |  3 ++
 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi      |  8 +++++
 board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 39 +++++++++++++++++++++
 configs/roc-pc-rk3399_defconfig             |  3 ++
 doc/board/rockchip/rockchip.rst             |  2 +-
 5 files changed, 54 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3399-roc-pc-plus-u-boot.dtsi

diff --git a/arch/arm/dts/rk3399-roc-pc-plus-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-plus-u-boot.dtsi
new file mode 100644
index 000000000000..c80529a62b97
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc-plus-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3399-roc-pc-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index a85e9549c83e..e7e4a2c89072 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -12,6 +12,14 @@
 	};
 };
 
+&i2c7 {
+	bootph-pre-ram;
+};
+
+&i2c7_xfer {
+	bootph-pre-ram;
+};
+
 &gpio4 {
 	bootph-pre-ram;
 };
diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
index 6937a27176f9..a12180e65573 100644
--- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
+++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
@@ -5,14 +5,24 @@
 
 #include <dm.h>
 #include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <image.h>
 #include <log.h>
 #include <spl_gpio.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 
 #include <asm/arch-rockchip/cru.h>
 #include <asm/arch-rockchip/gpio.h>
 #include <asm/arch-rockchip/grf_rk3399.h>
 
+#define ROC_PC_MP8859_BUS	"i2c@ff160000"
+#define ROC_PC_MP8859_ADDR	0x66
+#define ROC_PC_PLUS_FDTFILE	"rockchip/rk3399-roc-pc-plus.dtb"
+
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_XPL_BUILD
 
 #define PMUGRF_BASE	0xff320000
@@ -54,4 +64,33 @@ void led_setup(void)
 	spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
 }
 
+static bool is_roc_pc_plus(void)
+{
+	struct udevice *bus, *dev;
+
+	if (uclass_get_device_by_name(UCLASS_I2C, ROC_PC_MP8859_BUS, &bus))
+		return false;
+
+	return dm_i2c_probe(bus, ROC_PC_MP8859_ADDR, 0, &dev);
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	if (is_roc_pc_plus())
+		return strcmp(name, ROC_PC_PLUS_FDTFILE);
+
+	return strcmp(name, CONFIG_DEFAULT_FDT_FILE);
+}
+
 #endif
+
+int rk_board_late_init(void)
+{
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+				       "firefly,roc-rk3399-pc-plus"))
+		env_set("fdtfile", ROC_PC_PLUS_FDTFILE);
+	else
+		env_set("fdtfile", CONFIG_DEFAULT_FDT_FILE);
+
+	return 0;
+}
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 1df5cb03adbb..53182dc8251b 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -26,6 +26,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -37,6 +38,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="rockchip/rk3399-roc-pc rockchip/rk3399-roc-pc-plus"
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
@@ -49,6 +51,7 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 9351a5b8eae7..b565aea311e9 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -81,7 +81,7 @@ List of mainline supported Rockchip boards:
      - 96boards RK3399 Ficus (ficus-rk3399)
      - 96boards Rock960 (rock960-rk3399)
      - Firefly-RK3399 (firefly_rk3399)
-     - Firefly ROC-RK3399-PC
+     - Firefly ROC-RK3399-PC/ROC-RK3399-PC-PLUS (roc-pc-rk3399)
      - FriendlyElec NanoPC-T4 (nanopc-t4-rk3399)
      - FriendlyElec NanoPi M4 (nanopi-m4-rk3399)
      - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
-- 
2.43.0

Re: [PATCH v4 3/4] rockchip: rk3399: Add ROC-PC-PLUS board detection

[Quentin Schulz]

Hi Fabio,

On 7/22/26 9:46 PM, Fabio Estevam via U-Boot wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> The ROC-RK3399-PC has an MP8859 regulator on I2C7 at address 0x66,
> while the ROC-RK3399-PC-PLUS does not. Probe for the regulator in SPL
> and use the result to select the matching devicetree from the U-Boot
> FIT. Fall back to the original board if the I2C bus cannot be probed.
> 
> Build both devicetrees from the existing roc-pc-rk3399_defconfig and
> enable the XMC SPI NOR driver used by the Plus variant. Set fdtfile
> from the selected U-Boot devicetree so the matching Linux devicetree
> is used as well.
> 

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Thanks!
Quentin

[PATCH v4 4/4] rockchip: roc-pc-rk3399: Enable redundant environment

[Fabio Estevam via U-Boot]

From: Fabio Estevam <festevam@nabladev.com>

Keep the primary U-Boot environment at its existing 0x3f8000 offset and
use the preceding 32 KiB region at 0x3f0000 for the redundant copy.

Both copies are aligned to the 4 KiB erase size and together occupy
0x3f0000 through 0x3fffff. Redundancy protects the environment against
power loss or an interrupted update.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
Changes since v3:
- Preserved the primary environment at 0x3f8000.

 configs/roc-pc-rk3399_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 53182dc8251b..4347bab598ab 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0x3F0000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_DEBUG_UART=y
@@ -41,6 +42,7 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="rockchip/rk3399-roc-pc rockchip/rk3399-roc-pc-plus"
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_REDUNDANT=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-- 
2.43.0

Re: [PATCH v4 4/4] rockchip: roc-pc-rk3399: Enable redundant environment

[Quentin Schulz]

Hi Fabio,

On 7/22/26 9:46 PM, Fabio Estevam via U-Boot wrote:
> From: Fabio Estevam <festevam@nabladev.com>
> 
> Keep the primary U-Boot environment at its existing 0x3f8000 offset and
> use the preceding 32 KiB region at 0x3f0000 for the redundant copy.
> 
> Both copies are aligned to the 4 KiB erase size and together occupy
> 0x3f0000 through 0x3fffff. Redundancy protects the environment against
> power loss or an interrupted update.
> 

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Thanks!
Quentin

RE: [PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[Takahiro.Kuwano]

Hi,

> From: Fabio Estevam <festevam@nabladev.com>
> 
> Add the JEDEC ID for the XMC XM25QH128C SPI NOR flash.
> 
> This is a 128Mbit device using 64KiB sectors and supporting 4KiB
> erase, dual read and quad read, matching the other XM25QH128 variants.
> 
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---

It would be nice to have Link: tag followed by datasheet URL [1].

> Changes since v3:
> - None.
> 
>  drivers/mtd/spi/spi-nor-ids.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 31a2ba49a87c..90aa1025176c 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -673,6 +673,7 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> +       { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

Per the datasheet, this chip supports Dual/Quad ops but for my reference,
could you let me know if you tested 1-1-4 or 1-4-4 ops? 

Anyway,
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>

>         { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
>         { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
> --
> 2.43.0

[1] https://www.xmcwh.com/uploads/435/XM25QH128C.pdf

Re: [PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[Quentin Schulz via U-Boot]

Hi Fabio,

On 7/29/26 10:59 AM, Takahiro.Kuwano@infineon.com wrote:
> Hi,
> 
>> From: Fabio Estevam <festevam@nabladev.com>
>>
>> Add the JEDEC ID for the XMC XM25QH128C SPI NOR flash.
>>
>> This is a 128Mbit device using 64KiB sectors and supporting 4KiB
>> erase, dual read and quad read, matching the other XM25QH128 variants.
>>
>> Cc: Vignesh Raghavendra <vigneshr@ti.com>
>> Cc: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
>> ---
> 
> It would be nice to have Link: tag followed by datasheet URL [1].
> 

I'll add the link when applying (I'm targeting the next branch, open in 
a bit more than a week from now), no need to send a v5 for that.

Please still answer Takahiro's question below when you have time.

Thanks!
Quentin

>> Changes since v3:
>> - None.
>>
>>   drivers/mtd/spi/spi-nor-ids.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
>> index 31a2ba49a87c..90aa1025176c 100644
>> --- a/drivers/mtd/spi/spi-nor-ids.c
>> +++ b/drivers/mtd/spi/spi-nor-ids.c
>> @@ -673,6 +673,7 @@ const struct flash_info spi_nor_ids[] = {
>>          { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>>          { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>>          { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> +       { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> 
> Per the datasheet, this chip supports Dual/Quad ops but for my reference,
> could you let me know if you tested 1-1-4 or 1-4-4 ops?
> 
> Anyway,
> Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
> 
>>          { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>>          { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> SPI_NOR_4B_OPCODES) },
>>          { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>> SPI_NOR_4B_OPCODES) },
>> --
>> 2.43.0
> 
> [1] https://www.xmcwh.com/uploads/435/XM25QH128C.pdf
> 

Re: [PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[Fabio Estevam]

Hi Takahiro-san,

On Wed, Jul 29, 2026 at 5:59 AM <Takahiro.Kuwano@infineon.com> wrote:

> Per the datasheet, this chip supports Dual/Quad ops but for my reference,
> could you let me know if you tested 1-1-4 or 1-4-4 ops?

I checked the RK3399 SPI1 pin configuration. It only exposes CLK, CS,
TX/IO0, and RX/IO1; IO2 and IO3 are not muxed to the SPI controller.
Therefore, my test exercised 1-1-1 operations rather than either 1-1-4 or 1-4-4.

> Anyway,
> Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>

Thanks for the review.

RE: [PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[Takahiro.Kuwano]

> Hi Takahiro-san,
> 
> On Wed, Jul 29, 2026 at 5:59 AM <Takahiro.Kuwano@infineon.com> wrote:
> 
> > Per the datasheet, this chip supports Dual/Quad ops but for my reference,
> > could you let me know if you tested 1-1-4 or 1-4-4 ops?
> 
> I checked the RK3399 SPI1 pin configuration. It only exposes CLK, CS,
> TX/IO0, and RX/IO1; IO2 and IO3 are not muxed to the SPI controller.
> Therefore, my test exercised 1-1-1 operations rather than either 1-1-4 or 1-4-4.

Noted, thank you!

> 
> > Anyway,
> > Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
> 
> Thanks for the review.