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From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev,
	"Marc Zyngier" <maz@kernel.org>,
	"Oliver Upton" <oupton@kernel.org>
Subject: Re: [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI
Date: Fri, 24 Jul 2026 11:30:46 +0000	[thread overview]
Message-ID: <20260724113047.2B3021F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260724104819.1296803-20-sascha.bischoff@arm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The patch defines a new UAPI constant for configuring the GICv5 IRS address but provides no kernel implementation to handle it.
- [Low] UAPI macro KVM_VGIC_V5_IRS_SIZE uses the kernel-internal SZ_64K macro, causing compilation errors in userspace.
--

--- Patch [19]: [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI ---
commit 58ea54e3d864bdb3fe8fc046f0912b0e710377f8
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI

Define the UAPI address type used by userspace to describe the
location of the emulated IRS in guest physical address space, together
with the size reserved for that region.

As per the GICv5 specification, the IRS has one CONFIG_FRAME and
optionally one SETLPI_FRAME per interrupt domain. Within a KVM VM we
are only concerned with one interrupt domain. Each of these frames is
64kB in size, so reserve 2x64kB of contiguous memory in the GPA space
for a GICv5 IRS.

> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> index 1c13bfa2d38aa..d1b2ca317f586 100644
> --- a/arch/arm64/include/uapi/asm/kvm.h
> +++ b/arch/arm64/include/uapi/asm/kvm.h
> @@ -97,6 +97,11 @@ struct kvm_regs {
>  #define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)
>  #define KVM_VGIC_V3_ITS_SIZE		(2 * SZ_64K)
>  
> +/* Supported VGICv5 address types  */
> +#define KVM_VGIC_V5_ADDR_TYPE_IRS	6

[Severity: High]
Is this new UAPI attribute handled by the kernel?

Looking at vgic_v5_set_attr() in arch/arm64/kvm/vgic/vgic-kvm-device.c,
it currently returns -ENXIO for the KVM_DEV_ARM_VGIC_GRP_ADDR group:

arch/arm64/kvm/vgic/vgic-kvm-device.c:vgic_v5_set_attr() {
    ...
    case KVM_DEV_ARM_VGIC_GRP_ADDR:
    case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
    case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
        return -ENXIO;
    ...
}

Will userspace callers attempting to configure the IRS address via this
constant fail because the KVM_SET_DEVICE_ATTR ioctl path is unimplemented?

> +
> +#define KVM_VGIC_V5_IRS_SIZE		(2 * SZ_64K)

[Severity: Low]
Does this break userspace compilation?

The SZ_64K macro is a kernel-internal definition. If a userspace
application includes <asm/kvm.h> and references KVM_VGIC_V5_IRS_SIZE,
will it fail to compile due to an undeclared identifier?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=19

  reply	other threads:[~2026-07-24 11:30 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10   ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30   ` sashiko-bot [this message]
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45   ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-07-24 12:19   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-07-24 11:52   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-24 12:09   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-24 12:05   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 33/48] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-07-24 11:46   ` sashiko-bot
2026-07-24 10:57 ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-24 12:02   ` sashiko-bot
2026-07-24 10:57 ` [PATCH v4 36/48] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-24 12:19   ` sashiko-bot
2026-07-24 10:58 ` [PATCH v4 38/48] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 39/48] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 40/48] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-07-24 12:02   ` sashiko-bot
2026-07-24 10:59 ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-07-24 12:06   ` sashiko-bot
2026-07-24 10:59 ` [PATCH v4 43/48] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 44/48] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 45/48] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-07-24 12:15   ` sashiko-bot
2026-07-24 11:00 ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-07-24 12:18   ` sashiko-bot
2026-07-24 11:00 ` [PATCH v4 48/48] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff

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