From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvmarm@lists.linux.dev, "Marc Zyngier" <maz@kernel.org>,
"Oliver Upton" <oupton@kernel.org>,
kvm@vger.kernel.org
Subject: Re: [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS attribute tests
Date: Fri, 24 Jul 2026 12:02:40 +0000 [thread overview]
Message-ID: <20260724120240.C69B91F00A3E@smtp.kernel.org> (raw)
In-Reply-To: <20260724104819.1296803-42-sascha.bischoff@arm.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] The return value of `kvm_has_device_attr()` is silently ignored, rendering the attribute check ineffective.
- [Medium] The test for exceeding the maximum supported SPI count uses an unaligned value, failing to correctly verify the bounds check.
- [Medium] The test meant to verify that `NR_IRQS` is immutable after the VM has run is defeated by an explicit `CTRL_INIT` call.
--
--- Patch [41]: [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS attribute tests ---
commit 4c2364c5e2833c1962977d2e2805cafe763b427d
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
KVM: selftests: Add VGICv5 NR_IRQS attribute tests
Add coverage for the VGICv5 NR_IRQS attribute. VGICv5 exposes a
userspace-selectable SPI count, and KVM must reject values that cannot
be represented by the virtual IRS or that would change the interrupt
layout after it has been fixed.
> diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c b/tools/testing/selftests/kvm/arm64/vgic_v5.c
> index 51ea2fe7141ad..95d74f501ef09 100644
> --- a/tools/testing/selftests/kvm/arm64/vgic_v5.c
> +++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c
[ ... ]
> @@ -125,60 +183,106 @@ static void test_vgic_v5_create(void)
> vm_gic_destroy(&v);
> }
>
> -static void guest_irq_handler(struct ex_regs *regs)
> +static void test_vgic_v5_nr_irqs_attrs(void)
> {
> - bool valid;
> - u32 hwirq;
> - u64 ia;
> - static int count;
> -
> - /*
> - * We have pending interrupts. Should never actually enter WFI
> - * here!
> - */
> - wfi();
> - GUEST_SYNC(GUEST_CMD_IS_AWAKE);
> -
> - ia = gicr_insn(CDIA);
> - valid = GICV5_GICR_CDIA_VALID(ia);
> -
> - GUEST_SYNC(GUEST_CMD_IRQ_CDIA);
> + struct kvm_vcpu *vcpu;
> + struct vm_gic v;
> + uint64_t attr;
> + u32 nr_irqs;
> + int ret;
>
> - if (!valid)
> - return;
> + v.gic_dev_type = KVM_DEV_TYPE_ARM_VGIC_V5;
> + v.vm = __vm_create(VM_SHAPE_DEFAULT, NR_VCPUS, 0);
> + v.gic_fd = kvm_create_device(v.vm, v.gic_dev_type);
>
> - gsb_ack();
> - isb();
> + /* Check existing group/attribute */
> + kvm_has_device_attr(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0);
[Severity: Medium]
Is the return value of kvm_has_device_attr() intentionally ignored here?
If the attribute is missing, the test will proceed and fail on subsequent
operations rather than cleanly skipping or reporting the missing attribute.
Does this check need to be wrapped in a TEST_REQUIRE() or TEST_ASSERT()?
> +
> + /* Before userspace sets NR_IRQS, no SPI count has been selected. */
> + nr_irqs = 0xbad;
[ ... ]
> + /* Not a multiple of 32 */
> + nr_irqs = VGIC_V5_DEFAULT_NR_SPIS + 1;
> + ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
> + 0, &nr_irqs);
> + TEST_ASSERT(ret && errno == EINVAL, "GICv5 NR_IRQS not 32-aligned");
> +
> + /* Larger than KVM's supported VGICv5 SPI count */
> + nr_irqs = VGIC_V5_MAX_NR_SPIS + 1;
> + ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
> + 0, &nr_irqs);
> + TEST_ASSERT(ret && errno == EINVAL, "GICv5 NR_IRQS above maximum");
[Severity: Medium]
Will this check actually verify the maximum limit?
Since VGIC_V5_MAX_NR_SPIS (65536) + 1 is 65537, which is not a multiple of
32, the kernel will reject it with EINVAL due to the alignment constraint
before it reaches the maximum SPI limit check.
Should this test use VGIC_V5_MAX_NR_SPIS + 32 to ensure we test the upper
bound check rather than triggering the alignment check again?
> +
> + /* Valid custom SPI count */
> + nr_irqs = VGIC_V5_DEFAULT_NR_SPIS * 2;
[ ... ]
> + /* NR_IRQS must remain immutable after the VM has run. */
> + v.vm = __vm_create(VM_SHAPE_DEFAULT, NR_VCPUS, 0);
> + v.gic_fd = kvm_create_device(v.vm, v.gic_dev_type);
> + vcpu = vm_vcpu_add(v.vm, 0, guest_code);
>
> - gic_insn(hwirq, CDDI);
> - gic_insn(0, CDEOI);
> + attr = GICV5_IRS_CONFIG_BASE_GPA;
> + kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
> + KVM_VGIC_V5_ADDR_TYPE_IRS, &attr);
> + kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
> + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL);
>
> - GUEST_SYNC(GUEST_CMD_IRQ_DIEOI);
> + ret = run_vcpu(vcpu);
> + TEST_ASSERT(!ret, "Failed to run GICv5 VM before NR_IRQS test");
[Severity: Medium]
Does this explicit KVM_DEV_ARM_VGIC_CTRL_INIT call defeat the purpose of
testing if the attribute is immutable after the VM has run?
The previous test block already verifies that an explicit INIT locks the
NR_IRQS attribute. By calling it here before run_vcpu(), the subsequent
__kvm_device_attr_set() will return EBUSY solely because of this explicit
INIT, masking whether KVM_RUN actually implicitly locks the attribute as
intended.
>
> - if (++count >= 2)
> - GUEST_DONE();
> + nr_irqs = VGIC_V5_DEFAULT_NR_SPIS * 2;
> + ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
> + 0, &nr_irqs);
> + TEST_ASSERT(ret && errno == EBUSY, "GICv5 NR_IRQS set after run");
>
> - /* Ask for the next interrupt to be injected */
> - GUEST_SYNC(GUEST_CMD_IS_READY);
> -}
> + vm_gic_destroy(&v);
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=41
next prev parent reply other threads:[~2026-07-24 12:02 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21 ` sashiko-bot
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10 ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14 ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11 ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22 ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20 ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41 ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30 ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45 ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33 ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41 ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34 ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39 ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48 ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-07-24 12:19 ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-07-24 11:52 ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-24 12:09 ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-24 12:05 ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 33/48] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-07-24 11:46 ` sashiko-bot
2026-07-24 10:57 ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-24 12:02 ` sashiko-bot
2026-07-24 10:57 ` [PATCH v4 36/48] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-24 12:19 ` sashiko-bot
2026-07-24 10:58 ` [PATCH v4 38/48] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 39/48] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 40/48] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-07-24 12:02 ` sashiko-bot [this message]
2026-07-24 10:59 ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-07-24 12:06 ` sashiko-bot
2026-07-24 10:59 ` [PATCH v4 43/48] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 44/48] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 45/48] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-07-24 12:15 ` sashiko-bot
2026-07-24 11:00 ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-07-24 12:18 ` sashiko-bot
2026-07-24 11:00 ` [PATCH v4 48/48] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
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