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From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvmarm@lists.linux.dev, "Marc Zyngier" <maz@kernel.org>,
	"Oliver Upton" <oupton@kernel.org>,
	kvm@vger.kernel.org
Subject: Re: [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op
Date: Fri, 24 Jul 2026 11:39:32 +0000	[thread overview]
Message-ID: <20260724113933.01D4A1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260724104819.1296803-27-sascha.bischoff@arm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Incomplete state mirroring: hardware pending state desynchronizes from VGIC shadow state on guest MMIO/ITS writes.
- [Medium] Userspace-reachable WARN_ON_ONCE when set_pending_state fails, causing potential Denial of Service.
--

--- Patch [26]: [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op ---
commit f6a8b8f38eb780090a64d051bdb9d419dcf75e26
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic: Introduce set_pending_state() to irq_op

This patch introduces a set_pending_state() function pointer to irq_ops.
This allows the VGIC to communicate pending state directly to hardware for
cases where hardware manages parts of the interrupt lifecycle, like GICv5.
It wires this new callback into kvm_vgic_inject_irq().

> The intent is for this to be used after the VGIC shadow
> pending state has changed, allowing the backend to mirror the updated
> state into hardware.
>
> This new function is plumbed into kvm_vgic_inject_irq(), and is only
> called if irq_ops are provided and this function pointer is explicitly
> set.

[Severity: High]
If the intent is to mirror the state after the VGIC shadow pending state
has changed, should this also be wired up for guest MMIO writes and ITS
commands?

For example, when a guest writes to ISPENDR or ICPENDR, the shadow state is
updated in arch/arm64/kvm/vgic/vgic-mmio.c:__set_pending() and
__clear_pending(), but set_pending_state() is not called.

Similarly, in arch/arm64/kvm/vgic/vgic-its.c:vgic_its_cmd_handle_clear(),
the ITS CLEAR command updates the LPI pending state without notifying the
hardware.

Could this omission cause the hardware pending state to become desynchronized
from the VGIC shadow state, leading to missed or spurious interrupts?

> diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
> index 169a8664322d0..023792c28fc5c 100644
> --- a/arch/arm64/kvm/vgic/vgic.c
> +++ b/arch/arm64/kvm/vgic/vgic.c
> @@ -563,6 +563,9 @@ int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  	else
>  		irq->pending_latch = true;
>  
> +	if (irq->ops && irq->ops->set_pending_state)
> +		WARN_ON_ONCE(!irq->ops->set_pending_state(vcpu, irq));

[Severity: Medium]
Can a guest or unprivileged host-userspace trigger this warning?

Since kvm_vgic_inject_irq() is reachable via userspace injection
(e.g., KVM_IRQ_LINE) or guest actions, if an adversary can create
conditions that cause set_pending_state() to fail, they could trigger
this WARN_ON_ONCE. This would violate the KVM guideline against
user-reachable warnings.

Could this be replaced with a pr_warn_once() or handled by returning
an error code?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=26

  reply	other threads:[~2026-07-24 11:39 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10   ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30   ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45   ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39   ` sashiko-bot [this message]
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-07-24 12:19   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-07-24 11:52   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-24 12:09   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-24 12:05   ` sashiko-bot
2026-07-24 10:56 ` [PATCH v4 33/48] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-07-24 11:46   ` sashiko-bot
2026-07-24 10:57 ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-24 12:02   ` sashiko-bot
2026-07-24 10:57 ` [PATCH v4 36/48] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-24 12:19   ` sashiko-bot
2026-07-24 10:58 ` [PATCH v4 38/48] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 39/48] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 40/48] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-07-24 12:02   ` sashiko-bot
2026-07-24 10:59 ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-07-24 12:06   ` sashiko-bot
2026-07-24 10:59 ` [PATCH v4 43/48] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 44/48] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 45/48] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-07-24 12:15   ` sashiko-bot
2026-07-24 11:00 ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-07-24 12:18   ` sashiko-bot
2026-07-24 11:00 ` [PATCH v4 48/48] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff

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