From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org,
guodong@riscstar.com, dfustini@oss.tenstorrent.com,
michal.simek@amd.com, junhui.liu@pigmoral.tech,
darshan.prajapati@einfochips.com, akpm@linux-foundation.org,
zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com,
pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com,
jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com,
robin.randhawa@sifive.com, scott@riscstar.com,
dave.patel@riscstar.com, raymond.mao@riscstar.com,
anup@brainfault.org, pawandeep.oza@oss.qualcomm.com,
Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions
Date: Thu, 30 Jul 2026 00:39:06 +0800 [thread overview]
Message-ID: <20260729163908.249838-2-peter.lin@sifive.com> (raw)
In-Reply-To: <20260729163908.249838-1-peter.lin@sifive.com>
Add DT bindings for five RISC-V Worlds ISA extensions
that implement World ID tagging for hardware-enforced
context isolation. Also, add checks for extension
dependency requirements.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 2b0a8a93bb21..7a57191a0293 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -193,12 +193,35 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: smlwid
+ description: |
+ The standard Smlwid extension for M-mode control of lower
+ privilege World ID via the mlwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
+ - const: smlwidlist
+ description: |
+ The standard Smlwidlist extension for M-mode control of lower
+ privilege World IDs via the mlwidlist CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: smstateen
description: |
The standard Smstateen extension for controlling access to CSRs
added by other RISC-V extensions in H/S/VS/U/VU modes and as
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+ - const: smwiddeleg
+ description: |
+ The standard Smwiddeleg extension for M-mode delegation of lower
+ privilege World ID control to S-mode via the mwiddeleg CSR, as
+ ratified at commit TBD ("TBD") of riscv-worlds.
+
+ - const: smwid
+ description: |
+ The standard Smwid extension for M-mode World ID control via the
+ mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
@@ -262,6 +285,12 @@ properties:
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
+ - const: sswid
+ description: |
+ The standard Sswid extension for S-mode control of lower
+ privilege World IDs via the slwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: supm
description: |
The standard Supm extension for pointer masking support in user
@@ -924,6 +953,30 @@ properties:
then:
contains:
const: b
+ # Smlwidlist depends on Smwid and Smlwid
+ - if:
+ contains:
+ const: smlwidlist
+ then:
+ allOf:
+ - contains:
+ const: smwid
+ - contains:
+ const: smlwid
+ # Smwiddeleg depends on Smlwid
+ - if:
+ contains:
+ const: smwiddeleg
+ then:
+ contains:
+ const: smlwid
+ # Sswid depends on Smwiddeleg
+ - if:
+ contains:
+ const: sswid
+ then:
+ contains:
+ const: smwiddeleg
# Supm depends on Smnpm or Ssnpm
- if:
contains:
--
2.43.7
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org,
guodong@riscstar.com, dfustini@oss.tenstorrent.com,
michal.simek@amd.com, junhui.liu@pigmoral.tech,
darshan.prajapati@einfochips.com, akpm@linux-foundation.org,
zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com,
pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com,
jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com,
robin.randhawa@sifive.com, scott@riscstar.com,
dave.patel@riscstar.com, raymond.mao@riscstar.com,
anup@brainfault.org, pawandeep.oza@oss.qualcomm.com,
Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions
Date: Thu, 30 Jul 2026 00:39:06 +0800 [thread overview]
Message-ID: <20260729163908.249838-2-peter.lin@sifive.com> (raw)
In-Reply-To: <20260729163908.249838-1-peter.lin@sifive.com>
Add DT bindings for five RISC-V Worlds ISA extensions
that implement World ID tagging for hardware-enforced
context isolation. Also, add checks for extension
dependency requirements.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 2b0a8a93bb21..7a57191a0293 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -193,12 +193,35 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: smlwid
+ description: |
+ The standard Smlwid extension for M-mode control of lower
+ privilege World ID via the mlwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
+ - const: smlwidlist
+ description: |
+ The standard Smlwidlist extension for M-mode control of lower
+ privilege World IDs via the mlwidlist CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: smstateen
description: |
The standard Smstateen extension for controlling access to CSRs
added by other RISC-V extensions in H/S/VS/U/VU modes and as
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+ - const: smwiddeleg
+ description: |
+ The standard Smwiddeleg extension for M-mode delegation of lower
+ privilege World ID control to S-mode via the mwiddeleg CSR, as
+ ratified at commit TBD ("TBD") of riscv-worlds.
+
+ - const: smwid
+ description: |
+ The standard Smwid extension for M-mode World ID control via the
+ mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
@@ -262,6 +285,12 @@ properties:
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
+ - const: sswid
+ description: |
+ The standard Sswid extension for S-mode control of lower
+ privilege World IDs via the slwid CSR as ratified at commit
+ TBD ("TBD") of riscv-worlds.
+
- const: supm
description: |
The standard Supm extension for pointer masking support in user
@@ -924,6 +953,30 @@ properties:
then:
contains:
const: b
+ # Smlwidlist depends on Smwid and Smlwid
+ - if:
+ contains:
+ const: smlwidlist
+ then:
+ allOf:
+ - contains:
+ const: smwid
+ - contains:
+ const: smlwid
+ # Smwiddeleg depends on Smlwid
+ - if:
+ contains:
+ const: smwiddeleg
+ then:
+ contains:
+ const: smlwid
+ # Sswid depends on Smwiddeleg
+ - if:
+ contains:
+ const: sswid
+ then:
+ contains:
+ const: smwiddeleg
# Supm depends on Smnpm or Ssnpm
- if:
contains:
--
2.43.7
next prev parent reply other threads:[~2026-07-29 16:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` Yu-Chien Peter Lin [this message]
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-07-29 16:45 ` sashiko-bot
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 16:39 ` Yu-Chien Peter Lin
2026-07-29 16:52 ` sashiko-bot
2026-07-29 18:06 ` Rob Herring (Arm)
2026-07-29 18:06 ` Rob Herring (Arm)
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 16:39 ` Yu-Chien Peter Lin
2026-07-29 18:07 ` Rob Herring (Arm)
2026-07-29 18:07 ` Rob Herring (Arm)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260729163908.249838-2-peter.lin@sifive.com \
--to=peter.lin@sifive.com \
--cc=akpm@linux-foundation.org \
--cc=alex@ghiti.fr \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=darshan.prajapati@einfochips.com \
--cc=dave.patel@riscstar.com \
--cc=devicetree@vger.kernel.org \
--cc=dfustini@oss.tenstorrent.com \
--cc=dlan@kernel.org \
--cc=greentime.hu@sifive.com \
--cc=guodong@riscstar.com \
--cc=jim.shu@sifive.com \
--cc=junhui.liu@pigmoral.tech \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=luxu.kernel@bytedance.com \
--cc=michal.simek@amd.com \
--cc=nick.hu@sifive.com \
--cc=palmer@dabbelt.com \
--cc=pawandeep.oza@oss.qualcomm.com \
--cc=pincheng.plct@isrc.iscas.ac.cn \
--cc=pjw@kernel.org \
--cc=raymond.mao@riscstar.com \
--cc=robh@kernel.org \
--cc=robin.randhawa@sifive.com \
--cc=samuel.holland@sifive.com \
--cc=scott@riscstar.com \
--cc=zhangchunyan@iscas.ac.cn \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.