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From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org,
	guodong@riscstar.com, dfustini@oss.tenstorrent.com,
	michal.simek@amd.com, junhui.liu@pigmoral.tech,
	darshan.prajapati@einfochips.com, akpm@linux-foundation.org,
	zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com,
	pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com,
	jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com,
	robin.randhawa@sifive.com, scott@riscstar.com,
	dave.patel@riscstar.com, raymond.mao@riscstar.com,
	anup@brainfault.org, pawandeep.oza@oss.qualcomm.com,
	Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings
Date: Thu, 30 Jul 2026 00:39:05 +0800	[thread overview]
Message-ID: <20260729163908.249838-1-peter.lin@sifive.com> (raw)

Add device tree bindings for RISC-V Worlds, a standard extension that tags
every transaction with a World ID for fine-grained isolation. SiFive's
WorldGuard Checker is a hardware firewall in the system interconnect that
inspects transaction WIDs and enforces per-World access policies on memory
and MMIO devices.

wgChecker specification reference:
https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf

Yu-Chien Peter Lin (3):
  dt-bindings: riscv: Add Worlds ISA extensions
  dt-bindings: riscv: Add Worlds per-hart properties
  dt-bindings: sifive: Add WorldGuard Checker

 .../devicetree/bindings/riscv/cpus.yaml       |  61 +++
 .../devicetree/bindings/riscv/extensions.yaml |  53 +++
 .../devicetree/bindings/riscv/worlds.yaml     |  86 +++++
 .../bindings/sifive/sifive,wgchecker2.yaml    | 356 ++++++++++++++++++
 4 files changed, 556 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
 create mode 100644 Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml

-- 
2.43.7


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WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org,
	guodong@riscstar.com, dfustini@oss.tenstorrent.com,
	michal.simek@amd.com, junhui.liu@pigmoral.tech,
	darshan.prajapati@einfochips.com, akpm@linux-foundation.org,
	zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com,
	pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com,
	jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com,
	robin.randhawa@sifive.com, scott@riscstar.com,
	dave.patel@riscstar.com, raymond.mao@riscstar.com,
	anup@brainfault.org, pawandeep.oza@oss.qualcomm.com,
	Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings
Date: Thu, 30 Jul 2026 00:39:05 +0800	[thread overview]
Message-ID: <20260729163908.249838-1-peter.lin@sifive.com> (raw)

Add device tree bindings for RISC-V Worlds, a standard extension that tags
every transaction with a World ID for fine-grained isolation. SiFive's
WorldGuard Checker is a hardware firewall in the system interconnect that
inspects transaction WIDs and enforces per-World access policies on memory
and MMIO devices.

wgChecker specification reference:
https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf

Yu-Chien Peter Lin (3):
  dt-bindings: riscv: Add Worlds ISA extensions
  dt-bindings: riscv: Add Worlds per-hart properties
  dt-bindings: sifive: Add WorldGuard Checker

 .../devicetree/bindings/riscv/cpus.yaml       |  61 +++
 .../devicetree/bindings/riscv/extensions.yaml |  53 +++
 .../devicetree/bindings/riscv/worlds.yaml     |  86 +++++
 .../bindings/sifive/sifive,wgchecker2.yaml    | 356 ++++++++++++++++++
 4 files changed, 556 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
 create mode 100644 Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml

-- 
2.43.7


             reply	other threads:[~2026-07-29 16:39 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29 16:39 Yu-Chien Peter Lin [this message]
2026-07-29 16:39 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 16:45   ` sashiko-bot
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 16:52   ` sashiko-bot
2026-07-29 18:06   ` Rob Herring (Arm)
2026-07-29 18:06     ` Rob Herring (Arm)
2026-08-07  7:57     ` Yu-Chien Peter Lin
2026-08-07  7:57       ` Yu-Chien Peter Lin
2026-07-30  7:30   ` Krzysztof Kozlowski
2026-07-30  7:30     ` Krzysztof Kozlowski
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 18:07   ` Rob Herring (Arm)
2026-07-29 18:07     ` Rob Herring (Arm)
2026-07-30  7:35   ` Krzysztof Kozlowski
2026-07-30  7:35     ` Krzysztof Kozlowski
2026-07-30  7:37     ` Krzysztof Kozlowski
2026-07-30  7:37       ` Krzysztof Kozlowski
2026-07-30 17:36     ` Conor Dooley
2026-07-30 17:36       ` Conor Dooley
2026-07-31  1:43 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Nick Kossifidis
2026-07-31  1:43   ` Nick Kossifidis
2026-08-04  8:25   ` Yu-Chien Peter Lin
2026-08-04  8:25     ` Yu-Chien Peter Lin

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