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From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: "Rob Herring (Arm)" <robh@kernel.org>
Cc: anup@brainfault.org, guodong@riscstar.com,
	pincheng.plct@isrc.iscas.ac.cn, alex@ghiti.fr,
	aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, michal.simek@amd.com,
	dave.patel@riscstar.com, pjw@kernel.org,
	linux-riscv@lists.infradead.org, zhangchunyan@iscas.ac.cn,
	raymond.mao@riscstar.com, palmer@dabbelt.com,
	greentime.hu@sifive.com, dfustini@oss.tenstorrent.com,
	luxu.kernel@bytedance.com, conor+dt@kernel.org,
	akpm@linux-foundation.org, scott@riscstar.com,
	jim.shu@sifive.com, krzk+dt@kernel.org,
	robin.randhawa@sifive.com, zong.li@sifive.com,
	pawandeep.oza@oss.qualcomm.com, nick.hu@sifive.com,
	samuel.holland@sifive.com, darshan.prajapati@einfochips.com,
	junhui.liu@pigmoral.tech, dlan@kernel.org
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties
Date: Fri, 7 Aug 2026 15:57:20 +0800	[thread overview]
Message-ID: <anWP4Gyx9H3bMwUE@plin-1878> (raw)
In-Reply-To: <178534841698.3259786.10094204605740986474.robh@kernel.org>

Hi all,

On Wed, Jul 29, 2026 at 01:06:59PM -0500, Rob Herring (Arm) wrote:
> 
> On Thu, 30 Jul 2026 00:39:07 +0800, Yu-Chien Peter Lin wrote:
> > Add per-hart DT properties for the RISC-V Worlds architecture:
> > riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
> > platform-defined values are primarily used by M-mode firmware
> > to configure World ID CSRs and restrict WID usage across
> > privilege levels.
> > 
> > Also add schema validation rules to enforce valid property
> > combinations based on the ISA extensions present.
> > 
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> > ---
> >  .../devicetree/bindings/riscv/cpus.yaml       | 61 +++++++++++++++
> >  .../devicetree/bindings/riscv/worlds.yaml     | 77 +++++++++++++++++++
> >  2 files changed, 138 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@0 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@1 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@10 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@11 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml

I plan to remove the 'required' check for riscv,pmwid in the next
version. The riscv,pmwid property is intended to provide a valid
fallback when S-domain WID is not specified. This is a platform
integration responsibility, not a schema-enforced constraint.

The next version will only retain prohibitive checks — e.g., if the
smwid extension is absent, riscv,pmwidlist must not be present.

Regards,
Peter Lin

WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: "Rob Herring (Arm)" <robh@kernel.org>
Cc: anup@brainfault.org, guodong@riscstar.com,
	pincheng.plct@isrc.iscas.ac.cn, alex@ghiti.fr,
	aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, michal.simek@amd.com,
	dave.patel@riscstar.com, pjw@kernel.org,
	linux-riscv@lists.infradead.org, zhangchunyan@iscas.ac.cn,
	raymond.mao@riscstar.com, palmer@dabbelt.com,
	greentime.hu@sifive.com, dfustini@oss.tenstorrent.com,
	luxu.kernel@bytedance.com, conor+dt@kernel.org,
	akpm@linux-foundation.org, scott@riscstar.com,
	jim.shu@sifive.com, krzk+dt@kernel.org,
	robin.randhawa@sifive.com, zong.li@sifive.com,
	pawandeep.oza@oss.qualcomm.com, nick.hu@sifive.com,
	samuel.holland@sifive.com, darshan.prajapati@einfochips.com,
	junhui.liu@pigmoral.tech, dlan@kernel.org
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties
Date: Fri, 7 Aug 2026 15:57:20 +0800	[thread overview]
Message-ID: <anWP4Gyx9H3bMwUE@plin-1878> (raw)
In-Reply-To: <178534841698.3259786.10094204605740986474.robh@kernel.org>

Hi all,

On Wed, Jul 29, 2026 at 01:06:59PM -0500, Rob Herring (Arm) wrote:
> 
> On Thu, 30 Jul 2026 00:39:07 +0800, Yu-Chien Peter Lin wrote:
> > Add per-hart DT properties for the RISC-V Worlds architecture:
> > riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
> > platform-defined values are primarily used by M-mode firmware
> > to configure World ID CSRs and restrict WID usage across
> > privilege levels.
> > 
> > Also add schema validation rules to enforce valid property
> > combinations based on the ISA extensions present.
> > 
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> > ---
> >  .../devicetree/bindings/riscv/cpus.yaml       | 61 +++++++++++++++
> >  .../devicetree/bindings/riscv/worlds.yaml     | 77 +++++++++++++++++++
> >  2 files changed, 138 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@0 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@1 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@10 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
> Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@11 (riscv): 'riscv,pmwid' is a required property
> 	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml

I plan to remove the 'required' check for riscv,pmwid in the next
version. The riscv,pmwid property is intended to provide a valid
fallback when S-domain WID is not specified. This is a platform
integration responsibility, not a schema-enforced constraint.

The next version will only retain prohibitive checks — e.g., if the
smwid extension is absent, riscv,pmwidlist must not be present.

Regards,
Peter Lin

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-08-07  7:57 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 16:45   ` sashiko-bot
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 16:52   ` sashiko-bot
2026-07-29 18:06   ` Rob Herring (Arm)
2026-07-29 18:06     ` Rob Herring (Arm)
2026-08-07  7:57     ` Yu-Chien Peter Lin [this message]
2026-08-07  7:57       ` Yu-Chien Peter Lin
2026-07-30  7:30   ` Krzysztof Kozlowski
2026-07-30  7:30     ` Krzysztof Kozlowski
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 16:39   ` Yu-Chien Peter Lin
2026-07-29 18:07   ` Rob Herring (Arm)
2026-07-29 18:07     ` Rob Herring (Arm)
2026-07-30  7:35   ` Krzysztof Kozlowski
2026-07-30  7:35     ` Krzysztof Kozlowski
2026-07-30  7:37     ` Krzysztof Kozlowski
2026-07-30  7:37       ` Krzysztof Kozlowski
2026-07-30 17:36     ` Conor Dooley
2026-07-30 17:36       ` Conor Dooley
2026-07-31  1:43 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Nick Kossifidis
2026-07-31  1:43   ` Nick Kossifidis
2026-08-04  8:25   ` Yu-Chien Peter Lin
2026-08-04  8:25     ` Yu-Chien Peter Lin

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