From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: philmd@oss.qualcomm.com,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Brian Cain <brian.cain@oss.qualcomm.com>,
matheus.bernardino@oss.qualcomm.com
Subject: [PATCH v4 04/18] hw/hexagon: move the TLB to hex-subsys
Date: Wed, 29 Jul 2026 18:28:09 -0700 [thread overview]
Message-ID: <20260730012824.1135905-5-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260730012824.1135905-1-brian.cain@oss.qualcomm.com>
The TLB device is sized from the config table, so both machines create
it identically.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
include/hw/hexagon/hexagon.h | 1 +
hw/hexagon/hex-subsys.c | 16 ++++++++++++++++
hw/hexagon/hexagon_dsp.c | 10 ----------
hw/hexagon/virt.c | 10 ----------
4 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h
index ef5700082cc..6edd93f478a 100644
--- a/include/hw/hexagon/hexagon.h
+++ b/include/hw/hexagon/hexagon.h
@@ -158,6 +158,7 @@ struct HexagonCommonMachineState {
MemoryRegion cfgtable_rom;
MemoryRegion vtcm;
DeviceState *glob_regs;
+ DeviceState *tlb;
};
#endif
diff --git a/hw/hexagon/hex-subsys.c b/hw/hexagon/hex-subsys.c
index 6789b6bb23d..ac7e29604eb 100644
--- a/hw/hexagon/hex-subsys.c
+++ b/hw/hexagon/hex-subsys.c
@@ -9,6 +9,7 @@
#include "qapi/error.h"
#include "hw/hexagon/hex-subsys.h"
#include "hw/hexagon/hexagon_globalreg.h"
+#include "hw/hexagon/hexagon_tlb.h"
#include "hw/core/loader.h"
#include "hw/core/qdev-properties.h"
#include "hw/core/qdev.h"
@@ -29,6 +30,18 @@ static DeviceState *globalreg_create(HexagonCommonMachineState *hms,
return glob_regs;
}
+static DeviceState *tlb_create(HexagonCommonMachineState *hms,
+ const struct hexagon_machine_config *m_cfg)
+{
+ DeviceState *tlb = qdev_new(TYPE_HEXAGON_TLB);
+
+ object_property_add_child(OBJECT(hms), "tlb", OBJECT(tlb));
+ qdev_prop_set_uint32(tlb, "num-entries", m_cfg->cfgtable.jtlb_size_entries);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb), &error_fatal);
+
+ return tlb;
+}
+
void hex_subsys_create(HexagonCommonMachineState *hms,
const struct hexagon_machine_config *m_cfg, Rev_t rev)
{
@@ -57,11 +70,14 @@ void hex_subsys_create(HexagonCommonMachineState *hms,
}
hms->glob_regs = globalreg_create(hms, m_cfg, rev);
+ hms->tlb = tlb_create(hms, m_cfg);
}
void hex_subsys_realize_cpu(HexagonCommonMachineState *hms, DeviceState *cpu)
{
object_property_set_link(OBJECT(cpu), "global-regs",
OBJECT(hms->glob_regs), &error_fatal);
+ object_property_set_link(OBJECT(cpu), "tlb", OBJECT(hms->tlb),
+ &error_fatal);
qdev_realize_and_unref(cpu, NULL, &error_fatal);
}
diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c
index 8599f5883bf..25e8550fba2 100644
--- a/hw/hexagon/hexagon_dsp.c
+++ b/hw/hexagon/hexagon_dsp.c
@@ -15,7 +15,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/hexagon/hexagon.h"
#include "hw/hexagon/hex-subsys.h"
-#include "hw/hexagon/hexagon_tlb.h"
#include "hw/core/loader.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
@@ -108,7 +107,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
{
HexagonCommonMachineState *hms = HEXAGON_COMMON_MACHINE(machine);
HexagonDspMachineState *dms = HEXAGON_DSP_MACHINE(machine);
- DeviceState *tlb_dev;
memset(&hexagon_binfo, 0, sizeof(hexagon_binfo));
if (machine->kernel_filename) {
@@ -120,12 +118,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
hex_subsys_create(hms, m_cfg, rev);
- tlb_dev = qdev_new(TYPE_HEXAGON_TLB);
- object_property_add_child(OBJECT(machine), "tlb", OBJECT(tlb_dev));
- qdev_prop_set_uint32(tlb_dev, "num-entries",
- m_cfg->cfgtable.jtlb_size_entries);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb_dev), &error_fatal);
-
for (int i = 0; i < machine->smp.cpus; i++) {
HexagonCPU *cpu = HEXAGON_CPU(object_new(machine->cpu_type));
qemu_register_reset(do_cpu_reset, cpu);
@@ -138,8 +130,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
if (i == 0) {
hexagon_init_bootstrap(dms, cpu);
}
- object_property_set_link(OBJECT(cpu), "tlb",
- OBJECT(tlb_dev), &error_fatal);
hex_subsys_realize_cpu(hms, DEVICE(cpu));
}
}
diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c
index 290783d511f..b9e0bbb704c 100644
--- a/hw/hexagon/virt.c
+++ b/hw/hexagon/virt.c
@@ -14,7 +14,6 @@
#include "hw/core/sysbus-fdt.h"
#include "hw/hexagon/hexagon.h"
#include "hw/hexagon/hex-subsys.h"
-#include "hw/hexagon/hexagon_tlb.h"
#include "hw/core/loader.h"
#include "hw/core/qdev-properties.h"
#include "hw/core/qdev-clock.h"
@@ -225,7 +224,6 @@ static void virt_init(MachineState *ms)
{
HexagonVirtMachineState *vms = HEXAGON_VIRT_MACHINE(ms);
const struct hexagon_machine_config *m_cfg = &v68n_1024;
- DeviceState *tlb_dev;
int32_t clk_phandle;
create_fdt(vms);
@@ -248,12 +246,6 @@ static void virt_init(MachineState *ms)
fdt_add_hvx(vms, m_cfg);
- tlb_dev = qdev_new(TYPE_HEXAGON_TLB);
- object_property_add_child(OBJECT(ms), "tlb", OBJECT(tlb_dev));
- qdev_prop_set_uint32(tlb_dev, "num-entries",
- m_cfg->cfgtable.jtlb_size_entries);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb_dev), &error_fatal);
-
for (int i = 0; i < ms->smp.cpus; i++) {
HexagonCPU *cpu = HEXAGON_CPU(object_new(ms->cpu_type));
qemu_register_reset(do_cpu_reset, cpu);
@@ -269,8 +261,6 @@ static void virt_init(MachineState *ms)
}
qdev_prop_set_uint32(DEVICE(cpu), "htid", i);
qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i != 0));
- object_property_set_link(OBJECT(cpu), "tlb",
- OBJECT(tlb_dev), &error_fatal);
hex_subsys_realize_cpu(&vms->parent_obj, DEVICE(cpu));
}
--
2.34.1
next prev parent reply other threads:[~2026-07-30 1:30 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-30 1:28 [PATCH v4 00/18] Add hexagon l2vic, qtimer devices Brian Cain
2026-07-30 1:28 ` [PATCH v4 01/18] hw/hexagon: add hex-subsys Brian Cain
2026-07-31 17:28 ` Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 02/18] hw/hexagon: move VTCM to the common machine state Brian Cain
2026-07-31 17:29 ` Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 03/18] hw/hexagon: move global registers to hex-subsys Brian Cain
2026-07-31 17:29 ` Pierrick Bouvier
2026-07-30 1:28 ` Brian Cain [this message]
2026-07-31 17:30 ` [PATCH v4 04/18] hw/hexagon: move the TLB " Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 05/18] hw/hexagon: group the CPUs in a cluster Brian Cain
2026-07-31 17:34 ` Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 06/18] bitops.h: Add find_first_bit32() Brian Cain
2026-07-30 1:28 ` [PATCH v4 07/18] hw/intc: Add l2vic interrupt controller Brian Cain
2026-07-30 1:28 ` [PATCH v4 08/18] hw/hexagon: extract get_reg_value/set_reg_value stubs in globalreg Brian Cain
2026-07-30 1:28 ` [PATCH v4 09/18] hw/hexagon: connect l2vic device Brian Cain
2026-07-30 1:28 ` [PATCH v4 10/18] hw/hexagon/virt: instantiate virtio-mmio transports Brian Cain
2026-07-30 1:28 ` [PATCH v4 11/18] hw/hexagon/virt: add l2vic interrupt-controller and virtio-mmio FDT nodes Brian Cain
2026-07-31 17:35 ` Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 12/18] hw/hexagon/virt: connect pl011 UART interrupt Brian Cain
2026-07-30 1:28 ` [PATCH v4 13/18] tests/qtest: add L2VIC qtest Brian Cain
2026-07-30 1:28 ` [PATCH v4 14/18] tests/functional/hexagon: add arch_tests functional test Brian Cain
2026-07-30 1:28 ` [PATCH v4 15/18] hw/timer: Add QCT QTimer device model Brian Cain
2026-07-31 17:59 ` Pierrick Bouvier
2026-08-05 21:10 ` Brian Cain
2026-07-30 1:28 ` [PATCH v4 16/18] hw/hexagon: connect qtimer device Brian Cain
2026-07-31 17:36 ` Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 17/18] tests/qtest: add qct-qtimer qtest Brian Cain
2026-07-31 17:38 ` Pierrick Bouvier
2026-07-30 1:28 ` [PATCH v4 18/18] tests/functional/hexagon: enable more arch_tests cases Brian Cain
2026-07-31 17:39 ` Pierrick Bouvier
2026-07-31 17:42 ` Pierrick Bouvier
2026-08-03 15:43 ` Brian Cain
2026-08-04 21:35 ` Pierrick Bouvier
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