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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
	qemu-devel@nongnu.org
Cc: philmd@oss.qualcomm.com, Fabiano Rosas <farosas@suse.de>,
	Laurent Vivier <lvivier@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	matheus.bernardino@oss.qualcomm.com
Subject: Re: [PATCH v4 18/18] tests/functional/hexagon: enable more arch_tests cases
Date: Mon, 3 Aug 2026 10:43:20 -0500	[thread overview]
Message-ID: <6dfdd807-c6e7-4548-b4c0-73460295a7e7@oss.qualcomm.com> (raw)
In-Reply-To: <0c791fd2-f4d0-4f3e-8ad5-4d61ccd724fe@oss.qualcomm.com>


On 7/31/2026 12:42 PM, Pierrick Bouvier wrote:
> On 7/29/2026 6:28 PM, Brian Cain wrote:
>> Add more tests from hexagon-arch-tests, enabled by QTimer device.
>>
>> These exercise cache maintenance ops, l2vic, thread start/stop, tlb/mmu
>> operations, and user-mode transitions.
>>
>> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
>> ---
>>   tests/functional/hexagon/test_arch_tests.py | 32 +++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional/hexagon/test_arch_tests.py
>> index 2bb34f9b8dc..0834398c3b1 100755
>> --- a/tests/functional/hexagon/test_arch_tests.py
>> +++ b/tests/functional/hexagon/test_arch_tests.py
>> @@ -58,6 +58,38 @@ def test_int_steering(self) -> None:
>>           """
>>           self.run_uart_test("test_int_steering")
>>   
>> +    def test_cache(self) -> None:
>> +        """Tests cache operations: dckill/ickill, l2kill, dczeroa,
>> +        dccleaninva, cache disable/enable, barriers, and dcinva/dccleana.
>> +        """
>> +        self.run_uart_test("test_cache")
>> +
>> +    def test_l2vic(self) -> None:
>> +        """Tests the L2VIC interrupt controller: enable readback,
>> +        interrupt type readback, VID capture, and the fast interface.
>> +        """
>> +        self.run_uart_test("test_l2vic")
>> +
>> +    def test_threads(self) -> None:
>> +        """Tests hardware thread management: start/stop, MODECTL state,
>> +        per-thread HTID, shared memory, wait/resume, STID priority, and
>> +        SCHEDCFG/BESTWAIT readback.
>> +        """
>> +        self.run_uart_test("test_threads")
>> +
>> +    def test_tlb_mmu(self) -> None:
>> +        """Tests TLB/MMU operations: write/read/probe/invalidate,
>> +        global entries, multiple entries, overwrite, ASID matching,
>> +        and permission checks.
>> +        """
>> +        self.run_uart_test("test_tlb_mmu")
>> +
>> +    def test_user_mode(self) -> None:
>> +        """Tests user mode / privilege transitions: supervisor mode,
>> +        SSR UM/IE/XE/CE/PE bits, and the trap0 user-mode exit handler.
>> +        """
>> +        self.run_uart_test("test_user_mode")
>> +
>>   
>>   if __name__ == "__main__":
>>       QemuSystemTest.main()
> A general question on the pattern we have here.
>
> If those tests can be compiled with hexagon-cross container, would it
> make sense to add them to tcg/tests/hexagon/system directly in the future?
> Hopefully will be more easy once we have meson tcg-tests, so you don't
> need to add all dependencies by hand.


Glad you asked -- in a downstream fork, we originally did have several 
tests like these (not these particular ones but ~similar scope) running 
in check-tcg.  But we pivoted away from that because:

1. they're not testing merely translation: they depend on several sysemu 
devices.  More like integration/functional testing.

2. sometimes it's useful to verify not merely the exit code but also 
some output text to semihost/uart console.  This *can* be done with 
shell programs in make/meson, but it feels like "coloring outside of the 
lines."

3. most other architectures seem to have fairly ~light system emu 
check-tcg tests, perhaps because of #1/2?


We did this change with the assumption that these sysemu check-tcg tests 
wouldn't be welcomed by community because it diverges from what other 
targets do.  But maybe that was an overreaction?

It's certainly convenient to have test cases in-project so that changes 
to the tests don't require an indirect step to update a test code repo.  
So, we can do whatever best conforms to the project idioms in this 
regard.  Note that these particular tests in this patch are written in 
Rust and would introduce a new dependency (in the existing container, I 
suppose) beyond the C/C++ toolchain.  Fine w/me but food for thought.


>
> Regards,
> Pierrick


  reply	other threads:[~2026-08-03 15:44 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-30  1:28 [PATCH v4 00/18] Add hexagon l2vic, qtimer devices Brian Cain
2026-07-30  1:28 ` [PATCH v4 01/18] hw/hexagon: add hex-subsys Brian Cain
2026-07-31 17:28   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 02/18] hw/hexagon: move VTCM to the common machine state Brian Cain
2026-07-31 17:29   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 03/18] hw/hexagon: move global registers to hex-subsys Brian Cain
2026-07-31 17:29   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 04/18] hw/hexagon: move the TLB " Brian Cain
2026-07-31 17:30   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 05/18] hw/hexagon: group the CPUs in a cluster Brian Cain
2026-07-31 17:34   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 06/18] bitops.h: Add find_first_bit32() Brian Cain
2026-07-30  1:28 ` [PATCH v4 07/18] hw/intc: Add l2vic interrupt controller Brian Cain
2026-07-30  1:28 ` [PATCH v4 08/18] hw/hexagon: extract get_reg_value/set_reg_value stubs in globalreg Brian Cain
2026-07-30  1:28 ` [PATCH v4 09/18] hw/hexagon: connect l2vic device Brian Cain
2026-07-30  1:28 ` [PATCH v4 10/18] hw/hexagon/virt: instantiate virtio-mmio transports Brian Cain
2026-07-30  1:28 ` [PATCH v4 11/18] hw/hexagon/virt: add l2vic interrupt-controller and virtio-mmio FDT nodes Brian Cain
2026-07-31 17:35   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 12/18] hw/hexagon/virt: connect pl011 UART interrupt Brian Cain
2026-07-30  1:28 ` [PATCH v4 13/18] tests/qtest: add L2VIC qtest Brian Cain
2026-07-30  1:28 ` [PATCH v4 14/18] tests/functional/hexagon: add arch_tests functional test Brian Cain
2026-07-30  1:28 ` [PATCH v4 15/18] hw/timer: Add QCT QTimer device model Brian Cain
2026-07-31 17:59   ` Pierrick Bouvier
2026-08-05 21:10     ` Brian Cain
2026-07-30  1:28 ` [PATCH v4 16/18] hw/hexagon: connect qtimer device Brian Cain
2026-07-31 17:36   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 17/18] tests/qtest: add qct-qtimer qtest Brian Cain
2026-07-31 17:38   ` Pierrick Bouvier
2026-07-30  1:28 ` [PATCH v4 18/18] tests/functional/hexagon: enable more arch_tests cases Brian Cain
2026-07-31 17:39   ` Pierrick Bouvier
2026-07-31 17:42   ` Pierrick Bouvier
2026-08-03 15:43     ` Brian Cain [this message]
2026-08-04 21:35       ` Pierrick Bouvier

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