Re: [PATCH 04/22] arm64: dts: qcom: sc8180x: Fix the PCIe iommu-map entries

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Fixing `iommu-map` to use 5 cells breaks rigid 4-cell parsing in the `pcie-qcom.c` driver, corrupting PCIe SID translation.
--

--- Patch [4]: [PATCH 04/22] arm64: dts: qcom: sc8180x: Fix the PCIe iommu-map entries ---
commit 2707161425e0efca5af00d7a068414771d8112e9
Author: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

arm64: dts: qcom: sc8180x: Fix the PCIe iommu-map entries

This commit fixes the PCIe iommu-map entries to match the apps_smmu
provider's #iommu-cells = <2> property. It adds the missing SID mask cell to
prevent warnings from the OF core about 1-cell entries targeting 2-cell
outputs.

> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> @@ -1767,8 +1767,8 @@ pcie0: pcie@1c00000 {
>  			assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
>  			assigned-clock-rates = <19200000>;
>  
> -			iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
> -				    <0x100 &apps_smmu 0x1d81 0x1>;
> +			iommu-map = <0x0   &apps_smmu 0x1d80 0x0 0x1>,
> +				    <0x100 &apps_smmu 0x1d81 0x0 0x1>;

[Severity: High]
Does this change break the manual iommu-map parsing in the PCIe driver?

Looking at qcom_pcie_config_sid_1_9_0() in
drivers/pci/controller/dwc/pcie-qcom.c, the driver assumes a rigid 4-cell
length for iommu-map entries:

drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_config_sid_1_9_0() {
    ...
	struct {
		u32 bdf;
		u32 phandle;
		u32 smmu_sid;
		u32 smmu_sid_len;
	} *map;
    ...
	of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map,
				   size / sizeof(u32));
    ...
}

By increasing the iommu-map property to 5 cells per entry, will this misalign
the array when the driver parses multiple entries?

For the second entry here, map[1].bdf would read the 5th cell of the first
entry (length), map[1].phandle would read the BDF of the second entry, and
map[1].smmu_sid would read the phandle pointer.

Does this corrupt the SID translation and lead to IOMMU faults for downstream
PCIe endpoints?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260730-iommu-map-fix-v1-0-83405d37ba41@oss.qualcomm.com?part=4