Re: [PATCH 20/22] arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: Fix the PCIe iommu-map entries

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] The patch series successfully fixes incomplete `iommu-map` property entries for `qcs6490-thundercomm-minipc-g1iot.dts` and several other boards, but completely misses identical 4-cell entries targeting a 2-cell IOMMU provider in sibling board and devicetree files. The OF core will continue treating these maps as 1-cell output and emit warnings.
--

--- Patch [20]: [PATCH 20/22] arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: Fix the PCIe iommu-map entries ---
commit 8f2a940116e71ca780253365df0150f683e455ed
Author: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: Fix the PCIe iommu-map entries

The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe
iommu-map entries specify only one cell for the SID, omitting the SID
mask. This went unnoticed until the OF core started warning with commit
ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps").

> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
> --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
> @@ -711,15 +711,15 @@ &pcie1 {
>  		    <&pcie1_wake_n>;
>  	pinctrl-names = "default";
>  
> -	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> -		    <0x100 &apps_smmu 0x1c81 0x1>,
[ ... ]
> +	iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
> +		    <0x100 &apps_smmu 0x1c81 0x0 0x1>,
> +		    <0x208 &apps_smmu 0x1c84 0x0 0x1>,
> +		    <0x210 &apps_smmu 0x1c85 0x0 0x1>,
> +		    <0x218 &apps_smmu 0x1c86 0x0 0x1>,
> +		    <0x300 &apps_smmu 0x1c87 0x0 0x1>,
> +		    <0x400 &apps_smmu 0x1c88 0x0 0x1>,
> +		    <0x500 &apps_smmu 0x1c89 0x0 0x1>,
> +		    <0x501 &apps_smmu 0x1c90 0x0 0x1>;

[Severity: Medium]
This is a pre-existing issue, but since you are fixing the missing SID mask
for this board, should the identical malformed entries in other sibling boards
and devicetree files also be updated?

For example, in arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts for pcie1:

	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
		    <0x100 &apps_smmu 0x1c81 0x1>,

In arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso for pcie0
and pcie1:

	iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
		    <0x100 &apps_smmu 0x1c01 0x1>,

And in arch/arm/boot/dts/qcom/qcom-sdx55.dtsi for pcie_rc:

			iommu-map = <0x0   &apps_smmu 0x0200 0x1>,
				    <0x100 &apps_smmu 0x0201 0x1>,

Leaving these unfixed will continue to trigger the OF core warning about
1-cell entries targeting 2-cell #iommu-cells. Would it make sense to
include fixes for these files as well?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260730-iommu-map-fix-v1-0-83405d37ba41@oss.qualcomm.com?part=20