[PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Clément MATHIEU--DRIF]

SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
current implementation as it is already in line with the expected
behaviour.

Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
---
 hw/i386/intel_iommu.c          | 3 ++-
 hw/i386/intel_iommu_internal.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 8245452d89..9f21622a4f 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
     }
 
     if (s->svm) {
-        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
+        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
+                   VTD_ECAP_SMPWCS;
     }
 
     vtd_reset_caches(s);
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 924e91cb8a..df7a0efa6e 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -202,6 +202,7 @@
 #define VTD_ECAP_SMTS               (1ULL << 43)
 #define VTD_ECAP_SSTS               (1ULL << 46)
 #define VTD_ECAP_FSTS               (1ULL << 47)
+#define VTD_ECAP_SMPWCS             (1ULL << 48)
 
 /* CAP_REG */
 /* (offset >> 4) << 24 */
-- 
2.54.0

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Michael S. Tsirkin]

On Sun, Aug 02, 2026 at 04:05:08PM +0000, Clément MATHIEU--DRIF wrote:
> SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
> current implementation as it is already in line with the expected
> behaviour.
> 
> Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> ---
>  hw/i386/intel_iommu.c          | 3 ++-
>  hw/i386/intel_iommu_internal.h | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 8245452d89..9f21622a4f 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>      }
>  
>      if (s->svm) {
> -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> +                   VTD_ECAP_SMPWCS;
>      }
>  
>      vtd_reset_caches(s);
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 924e91cb8a..df7a0efa6e 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -202,6 +202,7 @@
>  #define VTD_ECAP_SMTS               (1ULL << 43)
>  #define VTD_ECAP_SSTS               (1ULL << 46)
>  #define VTD_ECAP_FSTS               (1ULL << 47)
> +#define VTD_ECAP_SMPWCS             (1ULL << 48)
>  
>  /* CAP_REG */
>  /* (offset >> 4) << 24 */

Any cross version migration concerns with this one?


> -- 
> 2.54.0

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Michael S. Tsirkin]

On Sun, Aug 02, 2026 at 04:05:08PM +0000, Clément MATHIEU--DRIF wrote:
> SVM in Linux requires SMPWC as of 780dfed68862.

And what is 780dfed68862?

> This is free in the
> current implementation as it is already in line with the expected
> behaviour.
> 
> Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> ---
>  hw/i386/intel_iommu.c          | 3 ++-
>  hw/i386/intel_iommu_internal.h | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 8245452d89..9f21622a4f 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>      }
>  
>      if (s->svm) {
> -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> +                   VTD_ECAP_SMPWCS;
>      }
>  
>      vtd_reset_caches(s);
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 924e91cb8a..df7a0efa6e 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -202,6 +202,7 @@
>  #define VTD_ECAP_SMTS               (1ULL << 43)
>  #define VTD_ECAP_SSTS               (1ULL << 46)
>  #define VTD_ECAP_FSTS               (1ULL << 47)
> +#define VTD_ECAP_SMPWCS             (1ULL << 48)
>  
>  /* CAP_REG */
>  /* (offset >> 4) << 24 */
> -- 
> 2.54.0

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Clément MATHIEU--DRIF]

On Sun, 2026-08-02 at 14:53 -0400, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> 
> 
> On Sun, Aug 02, 2026 at 04:05:08PM +0000, Clément MATHIEU--DRIF wrote:
> 
> > SVM in Linux requires SMPWC as of 780dfed68862.
> 
> 
> And what is 780dfed68862?

A commit in the linux tree, is there a dedicated tag for that?

Maybe "Link: link_to_github"?

> 
> 
> > This is free in the
> > current implementation as it is already in line with the expected
> > behaviour.
> > 
> > Signed-off-by: Clement Mathieu--Drif <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)>
> > ---
> >  hw/i386/intel_iommu.c          | 3 ++-
> >  hw/i386/intel_iommu_internal.h | 1 +
> >  2 files changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 8245452d89..9f21622a4f 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
> >      }
> > 
> >      if (s->svm) {
> > -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> > +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> > +                   VTD_ECAP_SMPWCS;
> >      }
> > 
> >      vtd_reset_caches(s);
> > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> > index 924e91cb8a..df7a0efa6e 100644
> > --- a/hw/i386/intel_iommu_internal.h
> > +++ b/hw/i386/intel_iommu_internal.h
> > @@ -202,6 +202,7 @@
> >  #define VTD_ECAP_SMTS               (1ULL << 43)
> >  #define VTD_ECAP_SSTS               (1ULL << 46)
> >  #define VTD_ECAP_FSTS               (1ULL << 47)
> > +#define VTD_ECAP_SMPWCS             (1ULL << 48)
> > 
> >  /* CAP_REG */
> >  /* (offset >> 4) << 24 */
> > --
> > 2.54.0
> 
> 

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Michael S. Tsirkin]

On Mon, Aug 03, 2026 at 05:40:06AM +0000, Clément MATHIEU--DRIF wrote:
> 
> 
> On Sun, 2026-08-02 at 14:53 -0400, Michael S. Tsirkin wrote:
> > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> > 
> > 
> > On Sun, Aug 02, 2026 at 04:05:08PM +0000, Clément MATHIEU--DRIF wrote:
> > 
> > > SVM in Linux requires SMPWC as of 780dfed68862.
> > 
> > 
> > And what is 780dfed68862?
> 
> A commit in the linux tree, is there a dedicated tag for that?
> 
> Maybe "Link: link_to_github"?

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=780dfed68862


> > 
> > 
> > > This is free in the
> > > current implementation as it is already in line with the expected
> > > behaviour.
> > > 
> > > Signed-off-by: Clement Mathieu--Drif <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)>
> > > ---
> > >  hw/i386/intel_iommu.c          | 3 ++-
> > >  hw/i386/intel_iommu_internal.h | 1 +
> > >  2 files changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > index 8245452d89..9f21622a4f 100644
> > > --- a/hw/i386/intel_iommu.c
> > > +++ b/hw/i386/intel_iommu.c
> > > @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
> > >      }
> > > 
> > >      if (s->svm) {
> > > -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> > > +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> > > +                   VTD_ECAP_SMPWCS;
> > >      }
> > > 
> > >      vtd_reset_caches(s);
> > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> > > index 924e91cb8a..df7a0efa6e 100644
> > > --- a/hw/i386/intel_iommu_internal.h
> > > +++ b/hw/i386/intel_iommu_internal.h
> > > @@ -202,6 +202,7 @@
> > >  #define VTD_ECAP_SMTS               (1ULL << 43)
> > >  #define VTD_ECAP_SSTS               (1ULL << 46)
> > >  #define VTD_ECAP_FSTS               (1ULL << 47)
> > > +#define VTD_ECAP_SMPWCS             (1ULL << 48)
> > > 
> > >  /* CAP_REG */
> > >  /* (offset >> 4) << 24 */
> > > --
> > > 2.54.0
> > 
> > 

RE: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Duan, Zhenzhong]

Hi Clement,

>-----Original Message-----
>From: Clément MATHIEU--DRIF <clement.mathieu--drif@bull.com>
>Subject: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled
>
>SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
>current implementation as it is already in line with the expected
>behaviour.

Not an issue in this patch, what about 'C: Page-walk Coherency' ecap bit,
I think we can enable it too? Maybe in another patch?

>
>Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
>---
> hw/i386/intel_iommu.c          | 3 ++-
> hw/i386/intel_iommu_internal.h | 1 +
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>index 8245452d89..9f21622a4f 100644
>--- a/hw/i386/intel_iommu.c
>+++ b/hw/i386/intel_iommu.c
>@@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>     }
>
>     if (s->svm) {
>-        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
>+        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
>+                   VTD_ECAP_SMPWCS;

I think we need a check for passthrough device to expose SMPWCS, something like below pseudo code:

@@ -37,6 +37,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,
         return false;
     }

+    if (VTD_ECAP_GET_SMPWCS(s->ecap) && !VTD_ECAP_GET_SMPWCS(vtd->cap_reg)) {
+        error_setg(errp,
+                   " Scalable-Mode Page-walk Coherency is unsupported by host IOMMU");
+        return false;
+    }
+
     if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) {
         error_setg(errp,
                    "First stage 1GB large page is unsupported by host IOMMU");

>     }
>
>     vtd_reset_caches(s);
>diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
>index 924e91cb8a..df7a0efa6e 100644
>--- a/hw/i386/intel_iommu_internal.h
>+++ b/hw/i386/intel_iommu_internal.h
>@@ -202,6 +202,7 @@
> #define VTD_ECAP_SMTS               (1ULL << 43)
> #define VTD_ECAP_SSTS               (1ULL << 46)
> #define VTD_ECAP_FSTS               (1ULL << 47)
>+#define VTD_ECAP_SMPWCS             (1ULL << 48)
>
> /* CAP_REG */
> /* (offset >> 4) << 24 */
>--
>2.54.0

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Yi Liu]

On 8/3/26 15:26, Duan, Zhenzhong wrote:
> Hi Clement,
> 
>> -----Original Message-----
>> From: Clément MATHIEU--DRIF <clement.mathieu--drif@bull.com>
>> Subject: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled
>>
>> SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
>> current implementation as it is already in line with the expected
>> behaviour.
> 
> Not an issue in this patch, what about 'C: Page-walk Coherency' ecap bit,
> I think we can enable it too? Maybe in another patch?
> 
>>
>> Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
>> ---
>> hw/i386/intel_iommu.c          | 3 ++-
>> hw/i386/intel_iommu_internal.h | 1 +
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index 8245452d89..9f21622a4f 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>>      }
>>
>>      if (s->svm) {
>> -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
>> +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
>> +                   VTD_ECAP_SMPWCS;
> 
> I think we need a check for passthrough device to expose SMPWCS, something like below pseudo code:

thumb up. yes.  It's strange guest reports SMPWCS while host does not.

> @@ -37,6 +37,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,
>           return false;
>       }
> 
> +    if (VTD_ECAP_GET_SMPWCS(s->ecap) && !VTD_ECAP_GET_SMPWCS(vtd->cap_reg)) {
> +        error_setg(errp,
> +                   " Scalable-Mode Page-walk Coherency is unsupported by host IOMMU");
> +        return false;
> +    }
> +
>       if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) {
>           error_setg(errp,
>                      "First stage 1GB large page is unsupported by host IOMMU");
> 
>>      }
>>
>>      vtd_reset_caches(s);
>> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
>> index 924e91cb8a..df7a0efa6e 100644
>> --- a/hw/i386/intel_iommu_internal.h
>> +++ b/hw/i386/intel_iommu_internal.h
>> @@ -202,6 +202,7 @@
>> #define VTD_ECAP_SMTS               (1ULL << 43)
>> #define VTD_ECAP_SSTS               (1ULL << 46)
>> #define VTD_ECAP_FSTS               (1ULL << 47)
>> +#define VTD_ECAP_SMPWCS             (1ULL << 48)
>>
>> /* CAP_REG */
>> /* (offset >> 4) << 24 */
>> --
>> 2.54.0

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Yi Liu]

On 8/3/26 00:05, Clément MATHIEU--DRIF wrote:
> SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
> current implementation as it is already in line with the expected
> behaviour.
> 
> Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> ---
>   hw/i386/intel_iommu.c          | 3 ++-
>   hw/i386/intel_iommu_internal.h | 1 +
>   2 files changed, 3 insertions(+), 1 deletion(-)

Is it a fix tag needed?

> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 8245452d89..9f21622a4f 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>       }
>   
>       if (s->svm) {
> -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> +                   VTD_ECAP_SMPWCS;
>       }
>   
>       vtd_reset_caches(s);
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 924e91cb8a..df7a0efa6e 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -202,6 +202,7 @@
>   #define VTD_ECAP_SMTS               (1ULL << 43)
>   #define VTD_ECAP_SSTS               (1ULL << 46)
>   #define VTD_ECAP_FSTS               (1ULL << 47)
> +#define VTD_ECAP_SMPWCS             (1ULL << 48)
>   
>   /* CAP_REG */
>   /* (offset >> 4) << 24 */

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Yi Liu]

On 8/3/26 00:47, Michael S. Tsirkin wrote:
> On Sun, Aug 02, 2026 at 04:05:08PM +0000, Clément MATHIEU--DRIF wrote:
>> SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
>> current implementation as it is already in line with the expected
>> behaviour.
>>
>> Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
>> ---
>>   hw/i386/intel_iommu.c          | 3 ++-
>>   hw/i386/intel_iommu_internal.h | 1 +
>>   2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index 8245452d89..9f21622a4f 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>>       }
>>   
>>       if (s->svm) {
>> -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
>> +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
>> +                   VTD_ECAP_SMPWCS;
>>       }
>>   
>>       vtd_reset_caches(s);
>> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
>> index 924e91cb8a..df7a0efa6e 100644
>> --- a/hw/i386/intel_iommu_internal.h
>> +++ b/hw/i386/intel_iommu_internal.h
>> @@ -202,6 +202,7 @@
>>   #define VTD_ECAP_SMTS               (1ULL << 43)
>>   #define VTD_ECAP_SSTS               (1ULL << 46)
>>   #define VTD_ECAP_FSTS               (1ULL << 47)
>> +#define VTD_ECAP_SMPWCS             (1ULL << 48)
>>   
>>   /* CAP_REG */
>>   /* (offset >> 4) << 24 */
> 
> Any cross version migration concerns with this one?

this bit is exposed when the svm flag is set. This flag was introduced
by the below commit and controlled by a 'svm' option. So looks like this
change is ok from the migration perspective?


952e1a6e90eb22a6deffa4e980277b135e9d077f

@@ -4186,6 +4188,7 @@ static const Property vtd_properties[] = {
      DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE),
      DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, 
false),
      DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
+    DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, false),
      DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
      DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),
      DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Clément MATHIEU--DRIF]

On Tue, 2026-08-04 at 16:51 +0800, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> 
> 
> On 8/3/26 00:47, Michael S. Tsirkin wrote:
> 
> > On Sun, Aug 02, 2026 at 04:05:08PM +0000, Clément MATHIEU--DRIF wrote:
> > 
> > > SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
> > > current implementation as it is already in line with the expected
> > > behaviour.
> > > 
> > > Signed-off-by: Clement Mathieu--Drif <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)>
> > > ---
> > >   hw/i386/intel_iommu.c          | 3 ++-
> > >   hw/i386/intel_iommu_internal.h | 1 +
> > >   2 files changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > index 8245452d89..9f21622a4f 100644
> > > --- a/hw/i386/intel_iommu.c
> > > +++ b/hw/i386/intel_iommu.c
> > > @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
> > >       }
> > > 
> > >       if (s->svm) {
> > > -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> > > +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> > > +                   VTD_ECAP_SMPWCS;
> > >       }
> > > 
> > >       vtd_reset_caches(s);
> > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> > > index 924e91cb8a..df7a0efa6e 100644
> > > --- a/hw/i386/intel_iommu_internal.h
> > > +++ b/hw/i386/intel_iommu_internal.h
> > > @@ -202,6 +202,7 @@
> > >   #define VTD_ECAP_SMTS               (1ULL << 43)
> > >   #define VTD_ECAP_SSTS               (1ULL << 46)
> > >   #define VTD_ECAP_FSTS               (1ULL << 47)
> > > +#define VTD_ECAP_SMPWCS             (1ULL << 48)
> > > 
> > >   /* CAP_REG */
> > >   /* (offset >> 4) << 24 */
> > 
> > 
> > Any cross version migration concerns with this one?
> 
> 
> this bit is exposed when the svm flag is set. This flag was introduced  
> by the below commit and controlled by a 'svm' option. So looks like this  
> change is ok from the migration perspective?

I came to the same conclusion.

Thanks

> 
> 
> 952e1a6e90eb22a6deffa4e980277b135e9d077f
> 
> @@ -4186,6 +4188,7 @@ static const Property vtd_properties[] = {  
>       DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE),  
>       DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control,  
> false),  
>       DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),  
> +    DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, false),  
>       DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),  
>       DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),  
>       DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),
> 

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Clément MATHIEU--DRIF]

On Tue, 2026-08-04 at 16:48 +0800, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> 
> 
> On 8/3/26 00:05, Clément MATHIEU--DRIF wrote:
> 
> > SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
> > current implementation as it is already in line with the expected
> > behaviour.
> > 
> > Signed-off-by: Clement Mathieu--Drif <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)>
> > ---
> >   hw/i386/intel_iommu.c          | 3 ++-
> >   hw/i386/intel_iommu_internal.h | 1 +
> >   2 files changed, 3 insertions(+), 1 deletion(-)
> 
> 
> Is it a fix tag needed?

Not sure, but we can add one in order to be consistent with the kernel commit.

> 
> 
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 8245452d89..9f21622a4f 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
> >       }
> > 
> >       if (s->svm) {
> > -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> > +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> > +                   VTD_ECAP_SMPWCS;
> >       }
> > 
> >       vtd_reset_caches(s);
> > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> > index 924e91cb8a..df7a0efa6e 100644
> > --- a/hw/i386/intel_iommu_internal.h
> > +++ b/hw/i386/intel_iommu_internal.h
> > @@ -202,6 +202,7 @@
> >   #define VTD_ECAP_SMTS               (1ULL << 43)
> >   #define VTD_ECAP_SSTS               (1ULL << 46)
> >   #define VTD_ECAP_FSTS               (1ULL << 47)
> > +#define VTD_ECAP_SMPWCS             (1ULL << 48)
> > 
> >   /* CAP_REG */
> >   /* (offset >> 4) << 24 */
> 
> 

Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

[Clément MATHIEU--DRIF]

On Tue, 2026-08-04 at 16:39 +0800, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> 
> 
> On 8/3/26 15:26, Duan, Zhenzhong wrote:
> 
> > Hi Clement,
> > 
> > 
> > > -----Original Message-----
> > > From: Clément MATHIEU--DRIF <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)>
> > > Subject: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled
> > > 
> > > SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
> > > current implementation as it is already in line with the expected
> > > behaviour.
> > 
> > 
> > Not an issue in this patch, what about 'C: Page-walk Coherency' ecap bit,
> > I think we can enable it too? Maybe in another patch?
> > 
> > 
> > > 
> > > Signed-off-by: Clement Mathieu--Drif <[clement.mathieu--drif@bull.com](mailto:clement.mathieu--drif@bull.com)>
> > > ---
> > > hw/i386/intel_iommu.c          | 3 ++-
> > > hw/i386/intel_iommu_internal.h | 1 +
> > > 2 files changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > index 8245452d89..9f21622a4f 100644
> > > --- a/hw/i386/intel_iommu.c
> > > +++ b/hw/i386/intel_iommu.c
> > > @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
> > >      }
> > > 
> > >      if (s->svm) {
> > > -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
> > > +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
> > > +                   VTD_ECAP_SMPWCS;
> > 
> > 
> > I think we need a check for passthrough device to expose SMPWCS, something like below pseudo code:
> 
> 
> thumb up. yes.  It's strange guest reports SMPWCS while host does not.

Will do,

thanks

> 
> 
> > @@ -37,6 +37,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,
> >           return false;
> >       }
> > 
> > +    if (VTD_ECAP_GET_SMPWCS(s->ecap) && !VTD_ECAP_GET_SMPWCS(vtd->cap_reg)) {
> > +        error_setg(errp,
> > +                   " Scalable-Mode Page-walk Coherency is unsupported by host IOMMU");
> > +        return false;
> > +    }
> > +
> >       if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) {
> >           error_setg(errp,
> >                      "First stage 1GB large page is unsupported by host IOMMU");
> > 
> > 
> > >      }
> > > 
> > >      vtd_reset_caches(s);
> > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> > > index 924e91cb8a..df7a0efa6e 100644
> > > --- a/hw/i386/intel_iommu_internal.h
> > > +++ b/hw/i386/intel_iommu_internal.h
> > > @@ -202,6 +202,7 @@
> > > #define VTD_ECAP_SMTS               (1ULL << 43)
> > > #define VTD_ECAP_SSTS               (1ULL << 46)
> > > #define VTD_ECAP_FSTS               (1ULL << 47)
> > > +#define VTD_ECAP_SMPWCS             (1ULL << 48)
> > > 
> > > /* CAP_REG */
> > > /* (offset >> 4) << 24 */
> > > --
> > > 2.54.0
> >
> 
>