[PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org
Subject: [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function
Date: Sun,  9 Aug 2026 15:35:03 -0700	[thread overview]
Message-ID: <20260809223545.730664-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20260809223545.730664-1-richard.henderson@linaro.org>

This allows each opcode table to be private to the decode file.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 disas/riscv-xlrbr.h    |  2 --
 disas/riscv-xthead.h   |  2 --
 disas/riscv-xventana.h |  2 --
 disas/riscv-xlrbr.c    |  4 +++-
 disas/riscv-xthead.c   | 13 ++++++++++++-
 disas/riscv-xventana.c |  3 ++-
 disas/riscv.c          | 34 +++++++++++++++++-----------------
 7 files changed, 34 insertions(+), 26 deletions(-)

diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h
index 939a69ea6d..ebf3d4c133 100644
--- a/disas/riscv-xlrbr.h
+++ b/disas/riscv-xlrbr.h
@@ -12,8 +12,6 @@
 
 #include "disas/riscv.h"
 
-extern const rv_opcode_data rv_xlrbr_opcode_data[];
-
 void decode_xlrbr(rv_decode *, rv_isa);
 
 #endif /* DISAS_RISCV_XLRBR_H */
diff --git a/disas/riscv-xthead.h b/disas/riscv-xthead.h
index fcd42746e7..0c65c8e0af 100644
--- a/disas/riscv-xthead.h
+++ b/disas/riscv-xthead.h
@@ -11,8 +11,6 @@
 
 #include "disas/riscv.h"
 
-extern const rv_opcode_data xthead_opcode_data[];
-
 void decode_xtheadba(rv_decode *, rv_isa);
 void decode_xtheadbb(rv_decode *, rv_isa);
 void decode_xtheadbs(rv_decode *, rv_isa);
diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h
index 72be9ffa16..1006c3be00 100644
--- a/disas/riscv-xventana.h
+++ b/disas/riscv-xventana.h
@@ -11,8 +11,6 @@
 
 #include "disas/riscv.h"
 
-extern const rv_opcode_data ventana_opcode_data[];
-
 void decode_xventanacondops(rv_decode*, rv_isa);
 
 #endif /* DISAS_RISCV_XVENTANA_H */
diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
index 57cb434523..f61028fce9 100644
--- a/disas/riscv-xlrbr.c
+++ b/disas/riscv-xlrbr.c
@@ -24,7 +24,7 @@ typedef enum {
     rv_op_crc32c_d = 8,
 } rv_xlrbr_op;
 
-const rv_opcode_data rv_xlrbr_opcode_data[] = {
+static const rv_opcode_data xlrbr_opcode_data[] = {
     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
     { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
@@ -75,5 +75,7 @@ void decode_xlrbr(rv_decode *dec, rv_isa isa)
         }
         break;
     }
+
+    dec->opcode_data = xlrbr_opcode_data;
     dec->op = op;
 }
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index 2f2ddb8dd9..96f80bc8e5 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -127,7 +127,7 @@ typedef enum {
     rv_op_th_sync_s,
 } rv_xthead_op;
 
-const rv_opcode_data xthead_opcode_data[] = {
+static const rv_opcode_data xthead_opcode_data[] = {
     { "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
     /* XTheadBa */
     { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
@@ -272,6 +272,7 @@ void decode_xtheadba(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -330,6 +331,7 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -356,6 +358,7 @@ void decode_xtheadbs(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -434,6 +437,7 @@ void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -461,6 +465,7 @@ void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -498,6 +503,7 @@ void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -533,6 +539,7 @@ void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -564,6 +571,7 @@ void decode_xtheadmac(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -638,6 +646,7 @@ void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -672,6 +681,7 @@ void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
 
@@ -706,5 +716,6 @@ void decode_xtheadsync(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = xthead_opcode_data;
     dec->op = op;
 }
diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
index cd694f15f3..4539173d95 100644
--- a/disas/riscv-xventana.c
+++ b/disas/riscv-xventana.c
@@ -14,7 +14,7 @@ typedef enum {
     ventana_op_vt_maskcn = 2,
 } rv_ventana_op;
 
-const rv_opcode_data ventana_opcode_data[] = {
+static const rv_opcode_data ventana_opcode_data[] = {
     { "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
     { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -38,5 +38,6 @@ void decode_xventanacondops(rv_decode *dec, rv_isa isa)
         break;
     }
 
+    dec->opcode_data = ventana_opcode_data;
     dec->op = op;
 }
diff --git a/disas/riscv.c b/disas/riscv.c
index 9880b8de20..eb6d132a2c 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1656,7 +1656,7 @@ static uint32_t operand_lpl(rv_inst inst)
 
 /* instruction metadata */
 
-const rv_opcode_data rvi_opcode_data[] = {
+static const rv_opcode_data rvi_opcode_data[] = {
     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
     { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
     { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
@@ -2948,6 +2948,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
 {
     rv_inst inst = dec->inst;
     rv_opcode op = rv_op_illegal;
+
     switch ((inst >> 0) & 0b11) {
     case 0:
         switch ((inst >> 13) & 0b111) {
@@ -4590,6 +4591,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
         }
         break;
     }
+
+    dec->opcode_data = rvi_opcode_data;
     dec->op = op;
 }
 
@@ -5421,33 +5424,30 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
     };
     const rv_opcode_data *op;
 
-    dec.opcode_data = rvi_opcode_data;
     decode_inst_opcode(&dec, isa);
 
     if (dec.op == rv_op_illegal && cfg) {
         static const struct {
             bool (*guard_func)(const RISCVCPUConfig *);
-            const rv_opcode_data *opcode_data;
             void (*decode_func)(rv_decode *, rv_isa);
         } decoders[] = {
-            { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
-            { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
-            { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
-            { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
-            { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
-            { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
-            { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
-            { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
-            { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
-            { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
-            { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
-            { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
-            { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
+            { has_xtheadba_p, decode_xtheadba },
+            { has_xtheadbb_p, decode_xtheadbb },
+            { has_xtheadbs_p, decode_xtheadbs },
+            { has_xtheadcmo_p, decode_xtheadcmo },
+            { has_xtheadcondmov_p, decode_xtheadcondmov },
+            { has_xtheadfmemidx_p, decode_xtheadfmemidx },
+            { has_xtheadfmv_p, decode_xtheadfmv },
+            { has_xtheadmac_p, decode_xtheadmac },
+            { has_xtheadmemidx_p, decode_xtheadmemidx },
+            { has_xtheadmempair_p, decode_xtheadmempair },
+            { has_xtheadsync_p, decode_xtheadsync },
+            { has_XVentanaCondOps_p, decode_xventanacondops },
+            { has_xlrbr_p, decode_xlrbr },
         };
 
         for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
             if (decoders[i].guard_func(cfg)) {
-                dec.opcode_data = decoders[i].opcode_data;
                 decoders[i].decode_func(&dec, isa);
                 if (dec.op != rv_op_illegal) {
                     break;
-- 
2.43.0

next prev parent reply	other threads:[~2026-08-09 22:42 UTC|newest]

Thread overview: 119+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
2026-08-11 19:54   ` Alistair
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
2026-08-11 19:55   ` Alistair
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
2026-08-10  2:53   ` Philippe Mathieu-Daudé
2026-08-11 19:56   ` Alistair
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
2026-08-11 19:57   ` Alistair
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
2026-08-11 19:58   ` Alistair
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
2026-08-11 19:59   ` Alistair
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
2026-08-10  2:54   ` Philippe Mathieu-Daudé
2026-08-11 19:59   ` Alistair
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
2026-08-10  2:54   ` Philippe Mathieu-Daudé
2026-08-11 20:00   ` Alistair
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
2026-08-11 20:02   ` Alistair
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
2026-08-11 20:04   ` Alistair
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:05   ` Alistair
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
2026-08-11 20:06   ` Alistair
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
2026-08-11 20:08   ` Alistair
2026-08-09 22:35 ` Richard Henderson [this message]
2026-08-11 20:09   ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Alistair
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
2026-08-11 20:10   ` Alistair
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
2026-08-10  2:55   ` Philippe Mathieu-Daudé
2026-08-11 20:10   ` Alistair
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
2026-08-11 20:11   ` Alistair
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
2026-08-11 20:12   ` Alistair
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
2026-08-11 20:14   ` Alistair
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
2026-08-11 20:14   ` Alistair
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
2026-08-11 20:16   ` Alistair
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
2026-08-11 20:16   ` Alistair
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
2026-08-11 20:17   ` Alistair
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
2026-08-11 20:17   ` Alistair
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
2026-08-11 20:18   ` Alistair
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
2026-08-10  2:58   ` Philippe Mathieu-Daudé
2026-08-11 20:19   ` Alistair
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
2026-08-11 20:20   ` Alistair
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
2026-08-11 20:21   ` Alistair
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
2026-08-11 20:22   ` Alistair
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
2026-08-11 20:23   ` Alistair
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
2026-08-11 20:23   ` Alistair
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:24   ` Alistair
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
2026-08-11 20:25   ` Alistair
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
2026-08-11 20:25   ` Alistair
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
2026-08-11 20:26   ` Alistair
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
2026-08-11 20:27   ` Alistair
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
2026-08-11 20:27   ` Alistair
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
2026-08-11 20:29   ` Alistair
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
2026-08-12 12:47   ` Alistair
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
2026-08-12 12:48   ` Alistair
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
2026-08-12 12:49   ` Alistair
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
2026-08-12 12:49   ` Alistair
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
2026-08-12 12:50   ` Alistair
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
2026-08-12 12:50   ` Alistair
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
2026-08-12 12:51   ` Alistair
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
2026-08-12 12:52   ` Alistair
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
2026-08-12 12:53   ` Alistair
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
2026-08-12 12:54   ` Alistair
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
2026-08-12 12:55   ` Alistair
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
2026-08-12 12:57   ` Alistair
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
2026-08-12 12:57   ` Alistair
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
2026-08-12 12:58   ` Alistair
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
2026-08-12 12:59   ` Alistair
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
2026-08-12 13:00   ` Alistair
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
2026-08-12 13:02   ` Alistair
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
2026-08-10  2:59   ` Philippe Mathieu-Daudé
2026-08-12 13:03   ` Alistair

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