From: Alistair <alistair@alistair23.me>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, TANG Tiancheng <lyndra@linux.alibaba.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 05/56] disas/riscv: Use extract helpers for operand fields
Date: Wed, 12 Aug 2026 05:58:41 +1000 [thread overview]
Message-ID: <d7ddde0569dba7ba79c23f86673be7923ac2ddac.camel@alistair23.me> (raw)
In-Reply-To: <20260809223545.730664-6-richard.henderson@linaro.org>
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> Replace shift-based operand extraction with extract32() and
> sextract32().
> For signed immediates, use sextract32() on the field that carries the
> sign
> bit and combine it with the remaining extract32() fields.
>
> The RISC-V disassembler currently follows target/riscv/internals.h:
> insn_len() and decodes only 16-bit or 32-bit instruction lengths, so
> the
> converted fields are all in the low 32 bits of rv_inst.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-5-84c566330bc7@linux.alib
> aba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 214 +++++++++++++++++++++++++-----------------------
> --
> 1 file changed, 107 insertions(+), 107 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 82b962dc71..2ba0a6a73a 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -4202,82 +4202,82 @@ static void decode_inst_opcode(rv_decode
> *dec, rv_isa isa)
>
> static uint32_t operand_rd(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_rs1(rv_inst inst)
> {
> - return (inst << 44) >> 59;
> + return extract32(inst, 15, 5);
> }
>
> static uint32_t operand_rs2(rv_inst inst)
> {
> - return (inst << 39) >> 59;
> + return extract32(inst, 20, 5);
> }
>
> static uint32_t operand_rs3(rv_inst inst)
> {
> - return (inst << 32) >> 59;
> + return extract32(inst, 27, 5);
> }
>
> static uint32_t operand_aq(rv_inst inst)
> {
> - return (inst << 37) >> 63;
> + return extract32(inst, 26, 1);
> }
>
> static uint32_t operand_rl(rv_inst inst)
> {
> - return (inst << 38) >> 63;
> + return extract32(inst, 25, 1);
> }
>
> static uint32_t operand_pred(rv_inst inst)
> {
> - return (inst << 36) >> 60;
> + return extract32(inst, 24, 4);
> }
>
> static uint32_t operand_succ(rv_inst inst)
> {
> - return (inst << 40) >> 60;
> + return extract32(inst, 20, 4);
> }
>
> static uint32_t operand_rm(rv_inst inst)
> {
> - return (inst << 49) >> 61;
> + return extract32(inst, 12, 3);
> }
>
> static uint32_t operand_shamt5(rv_inst inst)
> {
> - return (inst << 39) >> 59;
> + return extract32(inst, 20, 5);
> }
>
> static uint32_t operand_shamt6(rv_inst inst)
> {
> - return (inst << 38) >> 58;
> + return extract32(inst, 20, 6);
> }
>
> static uint32_t operand_shamt7(rv_inst inst)
> {
> - return (inst << 37) >> 57;
> + return extract32(inst, 20, 7);
> }
>
> static uint32_t operand_crdq(rv_inst inst)
> {
> - return (inst << 59) >> 61;
> + return extract32(inst, 2, 3);
> }
>
> static uint32_t operand_crs1q(rv_inst inst)
> {
> - return (inst << 54) >> 61;
> + return extract32(inst, 7, 3);
> }
>
> static uint32_t operand_crs1rdq(rv_inst inst)
> {
> - return (inst << 54) >> 61;
> + return extract32(inst, 7, 3);
> }
>
> static uint32_t operand_crs2q(rv_inst inst)
> {
> - return (inst << 59) >> 61;
> + return extract32(inst, 2, 3);
> }
>
> static uint32_t calculate_xreg(uint32_t sreg)
> @@ -4287,80 +4287,80 @@ static uint32_t calculate_xreg(uint32_t sreg)
>
> static uint32_t operand_sreg1(rv_inst inst)
> {
> - return calculate_xreg((inst << 54) >> 61);
> + return calculate_xreg(extract32(inst, 7, 3));
> }
>
> static uint32_t operand_sreg2(rv_inst inst)
> {
> - return calculate_xreg((inst << 59) >> 61);
> + return calculate_xreg(extract32(inst, 2, 3));
> }
>
> static uint32_t operand_crd(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_crs1(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_crs1rd(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_crs2(rv_inst inst)
> {
> - return (inst << 57) >> 59;
> + return extract32(inst, 2, 5);
> }
>
> static uint32_t operand_cimmsh5(rv_inst inst)
> {
> - return (inst << 57) >> 59;
> + return extract32(inst, 2, 5);
> }
>
> static uint32_t operand_csr12(rv_inst inst)
> {
> - return (inst << 32) >> 52;
> + return extract32(inst, 20, 12);
> }
>
> static int32_t operand_imm12(rv_inst inst)
> {
> - return ((int64_t)inst << 32) >> 52;
> + return sextract32(inst, 20, 12);
> }
>
> static int32_t operand_imm20(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 44) << 12;
> + return sextract32(inst, 12, 20) << 12;
> }
>
> static int32_t operand_jimm20(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 63) << 20 |
> - ((inst << 33) >> 54) << 1 |
> - ((inst << 43) >> 63) << 11 |
> - ((inst << 44) >> 56) << 12;
> + return sextract32(inst, 31, 1) << 20 |
> + extract32(inst, 21, 10) << 1 |
> + extract32(inst, 20, 1) << 11 |
> + extract32(inst, 12, 8) << 12;
> }
>
> static int32_t operand_simm12(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 57) << 5 |
> - (inst << 52) >> 59;
> + return sextract32(inst, 25, 7) << 5 |
> + extract32(inst, 7, 5);
> }
>
> static int32_t operand_sbimm12(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 63) << 12 |
> - ((inst << 33) >> 58) << 5 |
> - ((inst << 52) >> 60) << 1 |
> - ((inst << 56) >> 63) << 11;
> + return sextract32(inst, 31, 1) << 12 |
> + extract32(inst, 25, 6) << 5 |
> + extract32(inst, 8, 4) << 1 |
> + extract32(inst, 7, 1) << 11;
> }
>
> static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
> {
> - int imm = ((inst << 51) >> 63) << 5 |
> - (inst << 57) >> 59;
> + int imm = extract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> if (isa == rv128) {
> imm = imm ? imm : 64;
> }
> @@ -4369,8 +4369,8 @@ static uint32_t operand_cimmshl6(rv_inst inst,
> rv_isa isa)
>
> static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
> {
> - int imm = ((inst << 51) >> 63) << 5 |
> - (inst << 57) >> 59;
> + int imm = extract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> if (isa == rv128) {
> imm = imm | (imm & 32) << 1;
> imm = imm ? imm : 64;
> @@ -4380,116 +4380,116 @@ static uint32_t operand_cimmshr6(rv_inst
> inst, rv_isa isa)
>
> static int32_t operand_cimmi(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 5 |
> - (inst << 57) >> 59;
> + return sextract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> }
>
> static int32_t operand_cimmui(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 17 |
> - ((inst << 57) >> 59) << 12;
> + return sextract32(inst, 12, 1) << 17 |
> + extract32(inst, 2, 5) << 12;
> }
>
> static uint32_t operand_cimmlwsp(rv_inst inst)
> {
> - return ((inst << 51) >> 63) << 5 |
> - ((inst << 57) >> 61) << 2 |
> - ((inst << 60) >> 62) << 6;
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 4, 3) << 2 |
> + extract32(inst, 2, 2) << 6;
> }
>
> static uint32_t operand_cimmldsp(rv_inst inst)
> {
> - return ((inst << 51) >> 63) << 5 |
> - ((inst << 57) >> 62) << 3 |
> - ((inst << 59) >> 61) << 6;
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 5, 2) << 3 |
> + extract32(inst, 2, 3) << 6;
> }
>
> static uint32_t operand_cimmlqsp(rv_inst inst)
> {
> - return ((inst << 51) >> 63) << 5 |
> - ((inst << 57) >> 63) << 4 |
> - ((inst << 58) >> 60) << 6;
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 6, 1) << 4 |
> + extract32(inst, 2, 4) << 6;
> }
>
> static int32_t operand_cimm16sp(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 9 |
> - ((inst << 57) >> 63) << 4 |
> - ((inst << 58) >> 63) << 6 |
> - ((inst << 59) >> 62) << 7 |
> - ((inst << 61) >> 63) << 5;
> + return sextract32(inst, 12, 1) << 9 |
> + extract32(inst, 6, 1) << 4 |
> + extract32(inst, 5, 1) << 6 |
> + extract32(inst, 3, 2) << 7 |
> + extract32(inst, 2, 1) << 5;
> }
>
> static int32_t operand_cimmj(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 11 |
> - ((inst << 52) >> 63) << 4 |
> - ((inst << 53) >> 62) << 8 |
> - ((inst << 55) >> 63) << 10 |
> - ((inst << 56) >> 63) << 6 |
> - ((inst << 57) >> 63) << 7 |
> - ((inst << 58) >> 61) << 1 |
> - ((inst << 61) >> 63) << 5;
> + return sextract32(inst, 12, 1) << 11 |
> + extract32(inst, 11, 1) << 4 |
> + extract32(inst, 9, 2) << 8 |
> + extract32(inst, 8, 1) << 10 |
> + extract32(inst, 7, 1) << 6 |
> + extract32(inst, 6, 1) << 7 |
> + extract32(inst, 3, 3) << 1 |
> + extract32(inst, 2, 1) << 5;
> }
>
> static int32_t operand_cimmb(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 8 |
> - ((inst << 52) >> 62) << 3 |
> - ((inst << 57) >> 62) << 6 |
> - ((inst << 59) >> 62) << 1 |
> - ((inst << 61) >> 63) << 5;
> + return sextract32(inst, 12, 1) << 8 |
> + extract32(inst, 10, 2) << 3 |
> + extract32(inst, 5, 2) << 6 |
> + extract32(inst, 3, 2) << 1 |
> + extract32(inst, 2, 1) << 5;
> }
>
> static uint32_t operand_cimmswsp(rv_inst inst)
> {
> - return ((inst << 51) >> 60) << 2 |
> - ((inst << 55) >> 62) << 6;
> + return extract32(inst, 9, 4) << 2 |
> + extract32(inst, 7, 2) << 6;
> }
>
> static uint32_t operand_cimmsdsp(rv_inst inst)
> {
> - return ((inst << 51) >> 61) << 3 |
> - ((inst << 54) >> 61) << 6;
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 7, 3) << 6;
> }
>
> static uint32_t operand_cimmsqsp(rv_inst inst)
> {
> - return ((inst << 51) >> 62) << 4 |
> - ((inst << 53) >> 60) << 6;
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 7, 4) << 6;
> }
>
> static uint32_t operand_cimm4spn(rv_inst inst)
> {
> - return ((inst << 51) >> 62) << 4 |
> - ((inst << 53) >> 60) << 6 |
> - ((inst << 57) >> 63) << 2 |
> - ((inst << 58) >> 63) << 3;
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 7, 4) << 6 |
> + extract32(inst, 6, 1) << 2 |
> + extract32(inst, 5, 1) << 3;
> }
>
> static uint32_t operand_cimmw(rv_inst inst)
> {
> - return ((inst << 51) >> 61) << 3 |
> - ((inst << 57) >> 63) << 2 |
> - ((inst << 58) >> 63) << 6;
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 6, 1) << 2 |
> + extract32(inst, 5, 1) << 6;
> }
>
> static uint32_t operand_cimmd(rv_inst inst)
> {
> - return ((inst << 51) >> 61) << 3 |
> - ((inst << 57) >> 62) << 6;
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 5, 2) << 6;
> }
>
> static uint32_t operand_cimmq(rv_inst inst)
> {
> - return ((inst << 51) >> 62) << 4 |
> - ((inst << 53) >> 63) << 8 |
> - ((inst << 57) >> 62) << 6;
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 10, 1) << 8 |
> + extract32(inst, 5, 2) << 6;
> }
>
> static int32_t operand_vimm(rv_inst inst)
> {
> - return (int64_t)(inst << 44) >> 59;
> + return sextract32(inst, 15, 5);
> }
>
> static uint32_t operand_vuimm(rv_inst inst)
> @@ -4499,54 +4499,54 @@ static uint32_t operand_vuimm(rv_inst inst)
>
> static uint32_t operand_vzimm11(rv_inst inst)
> {
> - return (inst << 33) >> 53;
> + return extract32(inst, 20, 11);
> }
>
> static uint32_t operand_vzimm10(rv_inst inst)
> {
> - return (inst << 34) >> 54;
> + return extract32(inst, 20, 10);
> }
>
> static uint32_t operand_vzimm6(rv_inst inst)
> {
> - return ((inst << 37) >> 63) << 5 |
> - ((inst << 44) >> 59);
> + return extract32(inst, 26, 1) << 5 |
> + extract32(inst, 15, 5);
> }
>
> static uint32_t operand_bs(rv_inst inst)
> {
> - return (inst << 32) >> 62;
> + return extract32(inst, 30, 2);
> }
>
> static uint32_t operand_rnum(rv_inst inst)
> {
> - return (inst << 40) >> 60;
> + return extract32(inst, 20, 4);
> }
>
> static uint32_t operand_vm(rv_inst inst)
> {
> - return (inst << 38) >> 63;
> + return extract32(inst, 25, 1);
> }
>
> static uint32_t operand_uimm_c_lb(rv_inst inst)
> {
> - return (((inst << 58) >> 63) << 1) |
> - ((inst << 57) >> 63);
> + return extract32(inst, 5, 1) << 1 |
> + extract32(inst, 6, 1);
> }
>
> static uint32_t operand_uimm_c_lh(rv_inst inst)
> {
> - return (((inst << 58) >> 63) << 1);
> + return extract32(inst, 5, 1) << 1;
> }
>
> static uint32_t operand_zcmp_spimm(rv_inst inst)
> {
> - return ((inst << 60) >> 62) << 4;
> + return extract32(inst, 2, 2) << 4;
> }
>
> static uint32_t operand_zcmp_rlist(rv_inst inst)
> {
> - return ((inst << 56) >> 60);
> + return extract32(inst, 4, 4);
> }
>
> static uint32_t operand_imm6(rv_inst inst)
> @@ -4556,17 +4556,17 @@ static uint32_t operand_imm6(rv_inst inst)
>
> static uint32_t operand_imm2(rv_inst inst)
> {
> - return (inst << 37) >> 62;
> + return extract32(inst, 25, 2);
> }
>
> static uint32_t operand_immh(rv_inst inst)
> {
> - return (inst << 32) >> 58;
> + return extract32(inst, 26, 6);
> }
>
> static uint32_t operand_imml(rv_inst inst)
> {
> - return (inst << 38) >> 58;
> + return extract32(inst, 20, 6);
> }
>
> static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist,
> uint32_t spimm)
> @@ -4585,12 +4585,12 @@ static uint32_t
> operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
>
> static uint32_t operand_tbl_index(rv_inst inst)
> {
> - return ((inst << 54) >> 56);
> + return extract32(inst, 2, 8);
> }
>
> static uint32_t operand_lpl(rv_inst inst)
> {
> - return inst >> 12;
> + return extract32(inst, 12, 20);
> }
>
> /* decode operands */
next prev parent reply other threads:[~2026-08-11 19:58 UTC|newest]
Thread overview: 119+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
2026-08-11 19:54 ` Alistair
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
2026-08-11 19:55 ` Alistair
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
2026-08-10 2:53 ` Philippe Mathieu-Daudé
2026-08-11 19:56 ` Alistair
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
2026-08-11 19:57 ` Alistair
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
2026-08-11 19:58 ` Alistair [this message]
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 20:00 ` Alistair
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
2026-08-11 20:02 ` Alistair
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
2026-08-11 20:04 ` Alistair
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:05 ` Alistair
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
2026-08-11 20:06 ` Alistair
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
2026-08-11 20:08 ` Alistair
2026-08-09 22:35 ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Richard Henderson
2026-08-11 20:09 ` Alistair
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
2026-08-10 2:55 ` Philippe Mathieu-Daudé
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
2026-08-11 20:11 ` Alistair
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
2026-08-11 20:12 ` Alistair
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
2026-08-11 20:18 ` Alistair
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
2026-08-10 2:58 ` Philippe Mathieu-Daudé
2026-08-11 20:19 ` Alistair
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
2026-08-11 20:20 ` Alistair
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
2026-08-11 20:21 ` Alistair
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
2026-08-11 20:22 ` Alistair
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:24 ` Alistair
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
2026-08-11 20:26 ` Alistair
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
2026-08-11 20:29 ` Alistair
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
2026-08-12 12:47 ` Alistair
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
2026-08-12 12:48 ` Alistair
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
2026-08-12 12:51 ` Alistair
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
2026-08-12 12:52 ` Alistair
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
2026-08-12 12:53 ` Alistair
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
2026-08-12 12:54 ` Alistair
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
2026-08-12 12:55 ` Alistair
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
2026-08-12 12:58 ` Alistair
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
2026-08-12 12:59 ` Alistair
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
2026-08-12 13:00 ` Alistair
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
2026-08-12 13:02 ` Alistair
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
2026-08-10 2:59 ` Philippe Mathieu-Daudé
2026-08-12 13:03 ` Alistair
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