From: Alistair <alistair@alistair23.me>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org
Subject: Re: [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128}
Date: Wed, 12 Aug 2026 06:18:50 +1000 [thread overview]
Message-ID: <abaeb45abe24e9e59e8a0ce0eb3445cb31db4637.camel@alistair23.me> (raw)
In-Reply-To: <20260809223545.730664-26-richard.henderson@linaro.org>
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> We now distinguish compressed opcodes by isa during decode.
> Therefore we don't need 3 copies of decomp_*.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 4 +-
> disas/riscv.c | 155 ++++++++++++++++--------------------------------
> --
> 2 files changed, 51 insertions(+), 108 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 3909d73dd0..900363c603 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -183,9 +183,7 @@ typedef struct {
> rv_codec codec;
> const char *format;
> const rv_comp_data *pseudo;
> - short decomp_rv32;
> - short decomp_rv64;
> - short decomp_rv128;
> + rv_opcode decomp;
> } rv_opcode_data;
>
> typedef struct {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 95957506bd..2e891f509e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1883,91 +1883,52 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> - rv_op_addi, rv_op_addi },
> - { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> - rv_op_fld, 0 },
> - { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
> rv_op_lw,
> - rv_op_lw },
> - { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw, 0, 0 },
> - { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd,
> - rv_op_fsd, 0 },
> - { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
> rv_op_sw,
> - rv_op_sw },
> - { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0, 0 },
> + { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> + { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> + { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw
> },
> + { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> + { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> + { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw
> },
> + { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> { },
> - { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> - { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal,
> 0, 0 },
> - { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> - { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> - rv_op_addi, rv_op_addi },
> - { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui,
> rv_op_lui,
> - rv_op_lui },
> - { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srli,
> - rv_op_srli, rv_op_srli },
> - { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srai,
> - rv_op_srai, rv_op_srai },
> - { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL,
> rv_op_andi,
> - rv_op_andi, rv_op_andi },
> - { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub,
> rv_op_sub,
> - rv_op_sub },
> - { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor,
> rv_op_xor,
> - rv_op_xor },
> - { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or,
> rv_op_or,
> - rv_op_or },
> - { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and,
> rv_op_and,
> - rv_op_and },
> - { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw,
> rv_op_subw,
> - rv_op_subw },
> - { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw,
> rv_op_addw,
> - rv_op_addw },
> - { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal,
> rv_op_jal,
> - rv_op_jal },
> - { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq,
> rv_op_beq,
> - rv_op_beq },
> - { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne,
> rv_op_bne,
> - rv_op_bne },
> - { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_slli,
> - rv_op_slli, rv_op_slli },
> - { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> - rv_op_fld, rv_op_fld },
> - { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw,
> - rv_op_lw, rv_op_lw },
> - { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw, 0,
> - 0 },
> - { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr,
> - rv_op_jalr, rv_op_jalr },
> - { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> - { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
> - rv_op_ebreak, rv_op_ebreak },
> - { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr,
> - rv_op_jalr, rv_op_jalr },
> - { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add,
> rv_op_add,
> - rv_op_add },
> - { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd,
> - rv_op_fsd, rv_op_fsd },
> - { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw,
> - rv_op_sw, rv_op_sw },
> - { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0,
> - 0 },
> - { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0,
> rv_op_ld,
> - rv_op_ld },
> - { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0,
> rv_op_sd,
> - rv_op_sd },
> - { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0,
> rv_op_addiw,
> - rv_op_addiw },
> - { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0,
> rv_op_ld,
> - rv_op_ld },
> - { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> rv_op_sd,
> - rv_op_sd },
> - { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> - { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
> rv_op_sq },
> - { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> - { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> 0,
> - rv_op_sq },
> + { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> + { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal },
> + { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> + { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui },
> + { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli
> },
> + { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai
> },
> + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi
> },
> + { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub },
> + { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor },
> + { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or },
> + { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and },
> + { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw },
> + { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw },
> + { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal },
> + { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq
> },
> + { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne
> },
> + { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli
> },
> + { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> + { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw },
> + { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> + { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr
> },
> + { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi },
> + { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak
> },
> + { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr },
> + { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add },
> + { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> + { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw },
> + { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> + { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, rv_op_ld
> },
> + { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd
> },
> + { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addiw
> },
> + { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_ld },
> + { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sd },
> + { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, rv_op_lq
> },
> + { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq
> },
> + { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lq },
> + { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sq },
> { "nop", rv_codec_i, rv_fmt_none },
> { "mv", rv_codec_i, rv_fmt_rd_rs1 },
> { "not", rv_codec_i, rv_fmt_rd_rs1 },
> @@ -2649,10 +2610,8 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "ssrdp", rv_codec_r, rv_fmt_rd },
> { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
> - rv_op_sspush, 0 },
> - { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk,
> - rv_op_sspopchk, 0 },
> + { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush
> },
> + { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk },
> { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
> { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
> { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
> @@ -5397,24 +5356,10 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
>
> /* decompress instruction */
>
> -static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> rv_isa isa,
> +static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> const
> rv_opcode_data *op)
> {
> - int decomp_op;
> -
> - switch (isa) {
> - case rv32:
> - decomp_op = op->decomp_rv32;
> - break;
> - case rv64:
> - decomp_op = op->decomp_rv64;
> - break;
> - case rv128:
> - decomp_op = op->decomp_rv128;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> + int decomp_op = op->decomp;
>
> if (decomp_op != rv_op_illegal) {
> dec->op = decomp_op;
> @@ -5473,7 +5418,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>
> op = &dec.opcode_data[dec.op];
> decode_inst_operands(&dec, isa, op);
> - op = decode_inst_decompress(&dec, isa, op);
> + op = decode_inst_decompress(&dec, op);
> op = decode_inst_lift_pseudo(&dec, op);
> return format_inst(24, &dec, op);
> }
next prev parent reply other threads:[~2026-08-11 20:19 UTC|newest]
Thread overview: 119+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
2026-08-11 19:54 ` Alistair
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
2026-08-11 19:55 ` Alistair
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
2026-08-10 2:53 ` Philippe Mathieu-Daudé
2026-08-11 19:56 ` Alistair
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
2026-08-11 19:57 ` Alistair
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
2026-08-11 19:58 ` Alistair
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 20:00 ` Alistair
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
2026-08-11 20:02 ` Alistair
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
2026-08-11 20:04 ` Alistair
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:05 ` Alistair
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
2026-08-11 20:06 ` Alistair
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
2026-08-11 20:08 ` Alistair
2026-08-09 22:35 ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Richard Henderson
2026-08-11 20:09 ` Alistair
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
2026-08-10 2:55 ` Philippe Mathieu-Daudé
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
2026-08-11 20:11 ` Alistair
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
2026-08-11 20:12 ` Alistair
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
2026-08-11 20:18 ` Alistair [this message]
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
2026-08-10 2:58 ` Philippe Mathieu-Daudé
2026-08-11 20:19 ` Alistair
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
2026-08-11 20:20 ` Alistair
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
2026-08-11 20:21 ` Alistair
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
2026-08-11 20:22 ` Alistair
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:24 ` Alistair
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
2026-08-11 20:26 ` Alistair
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
2026-08-11 20:29 ` Alistair
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
2026-08-12 12:47 ` Alistair
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
2026-08-12 12:48 ` Alistair
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
2026-08-12 12:51 ` Alistair
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
2026-08-12 12:52 ` Alistair
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
2026-08-12 12:53 ` Alistair
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
2026-08-12 12:54 ` Alistair
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
2026-08-12 12:55 ` Alistair
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
2026-08-12 12:58 ` Alistair
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
2026-08-12 12:59 ` Alistair
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
2026-08-12 13:00 ` Alistair
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
2026-08-12 13:02 ` Alistair
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
2026-08-10 2:59 ` Philippe Mathieu-Daudé
2026-08-12 13:03 ` Alistair
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