[RFC PATCH v3 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings

[RFC PATCH v3 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings

[Yu-Chien Peter Lin]

This series introduces device tree bindings for the RISC-V Worlds ISA
extensions and the SiFive WorldGuard Checker hardware.

RISC-V Worlds is a set of standard ISA extensions (Smwid, Smlwid,
Smlwidlist, Smwiddeleg, Sswid) that enable hardware-enforced context
isolation by tagging each system transaction with a World ID (WID).
The extensions allow platform firmware to assign WIDs to privilege
levels, execution contexts, or isolation domains, and delegatable WID
management across privilege boundaries.

The SiFive WorldGuard Checker (wgChecker) is a hardware firewall
positioned in the system interconnect fabric. It inspects the WID
of every transaction and enforces access control policies on memory
regions and memory-mapped I/O devices. The wgChecker is based on the
access-controllers framework, allowing protected devices to declare
their access requirements via standard phandle references.

This is submitted as [RFC] because the RISC-V Worlds specification
is not yet ratified. The extension descriptions in extensions.yaml
carry placeholder "TBD" commit references; these will be updated
to the actual ratification commit before the series is merged.

Yu-Chien Peter Lin (3):
  dt-bindings: riscv: Add Worlds ISA extensions
  dt-bindings: riscv: Add Worlds per-hart properties
  dt-bindings: access-controllers: Add SiFive WorldGuard Checker

 .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++
 .../devicetree/bindings/riscv/cpus.yaml       |  44 +++++
 .../devicetree/bindings/riscv/extensions.yaml |  53 ++++++
 3 files changed, 275 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml

-- 
2.43.7

[RFC PATCH v3 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings

[Yu-Chien Peter Lin]

This series introduces device tree bindings for the RISC-V Worlds ISA
extensions and the SiFive WorldGuard Checker hardware.

RISC-V Worlds is a set of standard ISA extensions (Smwid, Smlwid,
Smlwidlist, Smwiddeleg, Sswid) that enable hardware-enforced context
isolation by tagging each system transaction with a World ID (WID).
The extensions allow platform firmware to assign WIDs to privilege
levels, execution contexts, or isolation domains, and delegatable WID
management across privilege boundaries.

The SiFive WorldGuard Checker (wgChecker) is a hardware firewall
positioned in the system interconnect fabric. It inspects the WID
of every transaction and enforces access control policies on memory
regions and memory-mapped I/O devices. The wgChecker is based on the
access-controllers framework, allowing protected devices to declare
their access requirements via standard phandle references.

This is submitted as [RFC] because the RISC-V Worlds specification
is not yet ratified. The extension descriptions in extensions.yaml
carry placeholder "TBD" commit references; these will be updated
to the actual ratification commit before the series is merged.

Yu-Chien Peter Lin (3):
  dt-bindings: riscv: Add Worlds ISA extensions
  dt-bindings: riscv: Add Worlds per-hart properties
  dt-bindings: access-controllers: Add SiFive WorldGuard Checker

 .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++
 .../devicetree/bindings/riscv/cpus.yaml       |  44 +++++
 .../devicetree/bindings/riscv/extensions.yaml |  53 ++++++
 3 files changed, 275 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml

-- 
2.43.7


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[RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions

[Yu-Chien Peter Lin]

Add DT bindings for RISC-V Worlds ISA extensions
(Smwid, Smlwidlist, Smlwid, Smwiddeleg, Sswid) and
enforce their architectural dependency rules in the
schema.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Add extension dependency rules
- Fix alphabetical order
---
 .../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 5ffc40d599c0..0408d1116527 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -181,6 +181,18 @@ properties:
             changes to interrupts as frozen at commit ccbddab ("Merge pull
             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
 
+        - const: smlwid
+          description: |
+            The standard Smlwid extension for M-mode control of lower
+            privilege World ID via the mlwid CSR as ratified at commit
+            TBD ("TBD") of riscv-worlds.
+
+        - const: smlwidlist
+          description: |
+            The standard Smlwidlist extension for M-mode control of lower
+            privilege World IDs via the mlwidlist CSR as ratified at commit
+            TBD ("TBD") of riscv-worlds.
+
         - const: smmpm
           description: |
             The standard Smmpm extension for M-mode pointer masking as
@@ -199,6 +211,17 @@ properties:
             added by other RISC-V extensions in H/S/VS/U/VU modes and as
             ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
 
+        - const: smwid
+          description: |
+            The standard Smwid extension for M-mode World ID control via the
+            mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
+
+        - const: smwiddeleg
+          description: |
+            The standard Smwiddeleg extension for M-mode delegation of lower
+            privilege World ID control to S-mode via the mwiddeleg CSR, as
+            ratified at commit TBD ("TBD") of riscv-worlds.
+
         - const: ssaia
           description: |
             The standard Ssaia supervisor-level extension for the advanced
@@ -262,6 +285,12 @@ properties:
             ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
             ("Updated to ratified state.")
 
+        - const: sswid
+          description: |
+            The standard Sswid extension for S-mode control of lower
+            privilege World IDs via the slwid CSR as ratified at commit
+            TBD ("TBD") of riscv-worlds.
+
         - const: supm
           description: |
             The standard Supm extension for pointer masking support in user
@@ -924,6 +953,30 @@ properties:
         then:
           contains:
             const: b
+      # Smlwidlist depends on Smwid and Smlwid
+      - if:
+          contains:
+            const: smlwidlist
+        then:
+          allOf:
+            - contains:
+                const: smwid
+            - contains:
+                const: smlwid
+      # Smwiddeleg depends on Smlwid
+      - if:
+          contains:
+            const: smwiddeleg
+        then:
+          contains:
+            const: smlwid
+      # Sswid depends on Smwiddeleg
+      - if:
+          contains:
+            const: sswid
+        then:
+          contains:
+            const: smwiddeleg
       # Supm depends on Smnpm or Ssnpm
       - if:
           contains:
-- 
2.43.7


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[RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions

[Yu-Chien Peter Lin]

Add DT bindings for RISC-V Worlds ISA extensions
(Smwid, Smlwidlist, Smlwid, Smwiddeleg, Sswid) and
enforce their architectural dependency rules in the
schema.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Add extension dependency rules
- Fix alphabetical order
---
 .../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 5ffc40d599c0..0408d1116527 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -181,6 +181,18 @@ properties:
             changes to interrupts as frozen at commit ccbddab ("Merge pull
             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
 
+        - const: smlwid
+          description: |
+            The standard Smlwid extension for M-mode control of lower
+            privilege World ID via the mlwid CSR as ratified at commit
+            TBD ("TBD") of riscv-worlds.
+
+        - const: smlwidlist
+          description: |
+            The standard Smlwidlist extension for M-mode control of lower
+            privilege World IDs via the mlwidlist CSR as ratified at commit
+            TBD ("TBD") of riscv-worlds.
+
         - const: smmpm
           description: |
             The standard Smmpm extension for M-mode pointer masking as
@@ -199,6 +211,17 @@ properties:
             added by other RISC-V extensions in H/S/VS/U/VU modes and as
             ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
 
+        - const: smwid
+          description: |
+            The standard Smwid extension for M-mode World ID control via the
+            mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds.
+
+        - const: smwiddeleg
+          description: |
+            The standard Smwiddeleg extension for M-mode delegation of lower
+            privilege World ID control to S-mode via the mwiddeleg CSR, as
+            ratified at commit TBD ("TBD") of riscv-worlds.
+
         - const: ssaia
           description: |
             The standard Ssaia supervisor-level extension for the advanced
@@ -262,6 +285,12 @@ properties:
             ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
             ("Updated to ratified state.")
 
+        - const: sswid
+          description: |
+            The standard Sswid extension for S-mode control of lower
+            privilege World IDs via the slwid CSR as ratified at commit
+            TBD ("TBD") of riscv-worlds.
+
         - const: supm
           description: |
             The standard Supm extension for pointer masking support in user
@@ -924,6 +953,30 @@ properties:
         then:
           contains:
             const: b
+      # Smlwidlist depends on Smwid and Smlwid
+      - if:
+          contains:
+            const: smlwidlist
+        then:
+          allOf:
+            - contains:
+                const: smwid
+            - contains:
+                const: smlwid
+      # Smwiddeleg depends on Smlwid
+      - if:
+          contains:
+            const: smwiddeleg
+        then:
+          contains:
+            const: smlwid
+      # Sswid depends on Smwiddeleg
+      - if:
+          contains:
+            const: sswid
+        then:
+          contains:
+            const: smwiddeleg
       # Supm depends on Smnpm or Ssnpm
       - if:
           contains:
-- 
2.43.7

[RFC PATCH v3 2/3] dt-bindings: riscv: Add Worlds per-hart properties

[Yu-Chien Peter Lin]

Add per-hart DT properties for the RISC-V Worlds architecture:
riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
platform-defined values are primarily used by M-mode firmware
to configure World ID CSRs and restrict WID usage across
privilege levels.

Also add schema validation rules to enforce valid property
combinations based on the ISA extensions present.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Drop riscv,nworlds property
- Drop 'required' check for riscv,pmwid
---
 .../devicetree/bindings/riscv/cpus.yaml       | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..326b68398b90 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,6 +39,26 @@ allOf:
       properties:
         thead,vlenb: false
 
+  - if:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: smwid
+    then:
+      properties:
+        riscv,pmwidlist: false
+
+  - if:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: smlwid
+    then:
+      properties:
+        riscv,pmlwidlist: false
+
 properties:
   compatible:
     oneOf:
@@ -113,6 +133,30 @@ properties:
     description:
       The blocksize in bytes for the Zicboz cache operations.
 
+  riscv,pmlwidlist:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description:
+      Optional bitmask of WIDs available for S-mode and U-mode use on this
+      hart; each set bit N indicates WID N is available. Firmware may read
+      this to select platform authorized WIDs for lower-privilege modes.
+
+  riscv,pmwid:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      M-mode World ID (WID) for this hart, M-mode firmware may read this
+      property to identify the WID for M-mode. For a Worlds-aware platform
+      without any Worlds ISA implemented, this is the WID for all privilege
+      modes.
+    minimum: 0
+    maximum: 63
+
+  riscv,pmwidlist:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description:
+      Optional bitmask of WIDs available for M-mode use on this hart; each
+      set bit N indicates WID N is available. Firmware may read this to
+      select a platform authorized WID.
+
   thead,vlenb:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
-- 
2.43.7


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[RFC PATCH v3 2/3] dt-bindings: riscv: Add Worlds per-hart properties

[Yu-Chien Peter Lin]

Add per-hart DT properties for the RISC-V Worlds architecture:
riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
platform-defined values are primarily used by M-mode firmware
to configure World ID CSRs and restrict WID usage across
privilege levels.

Also add schema validation rules to enforce valid property
combinations based on the ISA extensions present.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Drop riscv,nworlds property
- Drop 'required' check for riscv,pmwid
---
 .../devicetree/bindings/riscv/cpus.yaml       | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..326b68398b90 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,6 +39,26 @@ allOf:
       properties:
         thead,vlenb: false
 
+  - if:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: smwid
+    then:
+      properties:
+        riscv,pmwidlist: false
+
+  - if:
+      properties:
+        riscv,isa-extensions:
+          not:
+            contains:
+              const: smlwid
+    then:
+      properties:
+        riscv,pmlwidlist: false
+
 properties:
   compatible:
     oneOf:
@@ -113,6 +133,30 @@ properties:
     description:
       The blocksize in bytes for the Zicboz cache operations.
 
+  riscv,pmlwidlist:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description:
+      Optional bitmask of WIDs available for S-mode and U-mode use on this
+      hart; each set bit N indicates WID N is available. Firmware may read
+      this to select platform authorized WIDs for lower-privilege modes.
+
+  riscv,pmwid:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      M-mode World ID (WID) for this hart, M-mode firmware may read this
+      property to identify the WID for M-mode. For a Worlds-aware platform
+      without any Worlds ISA implemented, this is the WID for all privilege
+      modes.
+    minimum: 0
+    maximum: 63
+
+  riscv,pmwidlist:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description:
+      Optional bitmask of WIDs available for M-mode use on this hart; each
+      set bit N indicates WID N is available. Firmware may read this to
+      select a platform authorized WID.
+
   thead,vlenb:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
-- 
2.43.7

[RFC PATCH v3 3/3] dt-bindings: access-controllers: Add SiFive WorldGuard Checker

[Yu-Chien Peter Lin]

Add binding for the SiFive wgChecker, a programmable access controller
integrated in the interconnect fabric of RISC-V Worlds-capable SoCs.

At this initial stage, the binding is designed for M-mode firmware
to configure wgChecker partitions during platform initialization.
Linux typically runs as an untrusted World and does not require a
wgChecker driver; instead, it operates within the constraints enforced
by firmware-configured partitions.

wgChecker acts as an access-controllers provider, with consumers
(protected devices) referencing it via the standard access-controllers
phandle to declare their access requirements.

Link: https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Drop sifive,trustedwid property
- Reposition YAML file to bindings/access-controllers (Krzysztof)
- Fix compatible string (Krzysztof and Conor)
- Drop unneed description from stardard property (Krzysztof)
- Use consistent quotes (Krzysztof)
- Keep access controller provider node only (Krzysztof)
- Fix node name (Conor)
- Rename sifive,protected-region to sifive,wg-region
---
 .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++
 1 file changed, 178 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml

diff --git a/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml b/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml
new file mode 100644
index 000000000000..23ff7d6ef08e
--- /dev/null
+++ b/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2026 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/access-controllers/sifive,wgchecker2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive WorldGuard Checker
+
+maintainers:
+  - Yu-Chien Peter Lin <peter.lin@sifive.com>
+
+description: |
+  The RISC-V Worlds ISA extension defines World IDs (WIDs) as architectural
+  identifiers that tag each system transaction with its originating context.
+  System integrators assign WIDs to execution contexts such as privilege
+  modes, trusted execution environments, or other isolation boundaries.
+
+  The SiFive WorldGuard Checker is a hardware firewall positioned in the
+  system interconnect fabric. It supports up to 32 WIDs and inspects every
+  transaction, evaluating the WID against access control policies encoded
+  in checker slots for each protected resource. Transactions from
+  unauthorized WIDs are blocked and reported as bus errors, interrupts, or
+  both.
+
+  This enables spatial partitioning of memory regions and memory-mapped
+  devices across execution contexts. Different address ranges can enforce
+  distinct policies, allowing isolated workloads to coexist with
+  hardware-enforced protection.
+
+  The wgChecker acts as an access-controller provider as defined in the
+  access-controllers framework. Protected devices are consumers that
+  declare their access policy via the access-controllers property.
+
+allOf:
+  - $ref: /schemas/access-controllers/access-controllers.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qemu,wgchecker2
+      - const: sifive,wgchecker2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description:
+      Interrupt line asserted when a WID access violation is detected and
+      interrupt reporting is enabled in the slot configuration (IR or IW
+      bits set).
+
+  "#access-controller-cells":
+    const: 1
+    description: |
+      Specifies the partition identifier to reference a partition child
+      node that defines the access control region, WID permissions, and
+      access failure configuration. The special ID 0xFFFFFFFF indicates
+      unprotected mode, granting unrestricted access to the device.
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^partition@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+
+    properties:
+      reg:
+        maximum: 0xFFFFFFFE
+        description:
+          Partition identifier. Must be unique within the wgChecker node.
+          The value 0xFFFFFFFF is reserved for unprotected mode and must
+          not be used.
+
+      sifive,wg-region:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description:
+          Protected memory region encoded as a base address and size.
+        items:
+          - description: Upper 32 bits of the base address
+          - description: Lower 32 bits of the base address
+          - description: Upper 32 bits of the region size
+          - description: Lower 32 bits of the region size
+
+      sifive,slot-permissions:
+        $ref: /schemas/types.yaml#/definitions/uint64
+        description: |
+          64-bit WID permission bitmap. Each WID N uses two consecutive bits:
+            - bit[2*N]  : Read  permission for WID N
+            - bit[2*N+1]: Write permission for WID N
+          Set bits grant access.
+
+      sifive,slot-config:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 0x1F
+        description: |
+          Access failure configuration flags for this slot:
+            bit[0] (ER): report read  violations as bus errors
+            bit[1] (EW): report write violations as bus errors
+            bit[2] (IR): report read  violations via interrupt
+            bit[3] (IW): report write violations via interrupt
+            bit[4] (L) : lock this slot against further modification
+          Bits[5:31] are reserved and must be zero.
+
+    required:
+      - reg
+      - sifive,wg-region
+      - sifive,slot-permissions
+      - sifive,slot-config
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - "#access-controller-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    // Example 1: Peripheral device protection
+
+    access-controller@c1000 {
+        compatible = "qemu,wgchecker2", "sifive,wgchecker2";
+        reg = <0xc1000 0x1000>;
+        #access-controller-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <80 4>;
+
+        partition@0 {
+            reg = <0>;
+            sifive,wg-region = <0x0 0x000c0000 0x0 0x00001000>;
+            sifive,slot-permissions = <0x0 0x000000c3>;
+            sifive,slot-config = <0x0f>;
+        };
+    };
+
+  - |
+    // Example 2: DRAM partitioning with multiple regions
+
+    access-controller@40000000 {
+        compatible = "qemu,wgchecker2", "sifive,wgchecker2";
+        reg = <0x40000000 0x1000>;
+        #access-controller-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <82 4>;
+
+        partition@0 {
+            reg = <0>;
+            sifive,wg-region = <0x0 0x80000000 0x0 0x40000000>;
+            sifive,slot-permissions = <0x0 0x000000cf>;
+            sifive,slot-config = <0x0f>;
+        };
+
+        partition@1 {
+            reg = <1>;
+            sifive,wg-region = <0x0 0xc0000000 0x0 0x01000000>;
+            sifive,slot-permissions = <0x0 0x000000cc>;
+            sifive,slot-config = <0x0f>;
+        };
+
+        partition@2 {
+            reg = <2>;
+            sifive,wg-region = <0x0 0xc1000000 0x0 0x3f000000>;
+            sifive,slot-permissions = <0x0 0x000000cf>;
+            sifive,slot-config = <0x0f>;
+        };
+    };
-- 
2.43.7


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[RFC PATCH v3 3/3] dt-bindings: access-controllers: Add SiFive WorldGuard Checker

[Yu-Chien Peter Lin]

Add binding for the SiFive wgChecker, a programmable access controller
integrated in the interconnect fabric of RISC-V Worlds-capable SoCs.

At this initial stage, the binding is designed for M-mode firmware
to configure wgChecker partitions during platform initialization.
Linux typically runs as an untrusted World and does not require a
wgChecker driver; instead, it operates within the constraints enforced
by firmware-configured partitions.

wgChecker acts as an access-controllers provider, with consumers
(protected devices) referencing it via the standard access-controllers
phandle to declare their access requirements.

Link: https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Changes v2->v3:
- Drop sifive,trustedwid property
- Reposition YAML file to bindings/access-controllers (Krzysztof)
- Fix compatible string (Krzysztof and Conor)
- Drop unneed description from stardard property (Krzysztof)
- Use consistent quotes (Krzysztof)
- Keep access controller provider node only (Krzysztof)
- Fix node name (Conor)
- Rename sifive,protected-region to sifive,wg-region
---
 .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++
 1 file changed, 178 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml

diff --git a/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml b/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml
new file mode 100644
index 000000000000..23ff7d6ef08e
--- /dev/null
+++ b/Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2026 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/access-controllers/sifive,wgchecker2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive WorldGuard Checker
+
+maintainers:
+  - Yu-Chien Peter Lin <peter.lin@sifive.com>
+
+description: |
+  The RISC-V Worlds ISA extension defines World IDs (WIDs) as architectural
+  identifiers that tag each system transaction with its originating context.
+  System integrators assign WIDs to execution contexts such as privilege
+  modes, trusted execution environments, or other isolation boundaries.
+
+  The SiFive WorldGuard Checker is a hardware firewall positioned in the
+  system interconnect fabric. It supports up to 32 WIDs and inspects every
+  transaction, evaluating the WID against access control policies encoded
+  in checker slots for each protected resource. Transactions from
+  unauthorized WIDs are blocked and reported as bus errors, interrupts, or
+  both.
+
+  This enables spatial partitioning of memory regions and memory-mapped
+  devices across execution contexts. Different address ranges can enforce
+  distinct policies, allowing isolated workloads to coexist with
+  hardware-enforced protection.
+
+  The wgChecker acts as an access-controller provider as defined in the
+  access-controllers framework. Protected devices are consumers that
+  declare their access policy via the access-controllers property.
+
+allOf:
+  - $ref: /schemas/access-controllers/access-controllers.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qemu,wgchecker2
+      - const: sifive,wgchecker2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description:
+      Interrupt line asserted when a WID access violation is detected and
+      interrupt reporting is enabled in the slot configuration (IR or IW
+      bits set).
+
+  "#access-controller-cells":
+    const: 1
+    description: |
+      Specifies the partition identifier to reference a partition child
+      node that defines the access control region, WID permissions, and
+      access failure configuration. The special ID 0xFFFFFFFF indicates
+      unprotected mode, granting unrestricted access to the device.
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^partition@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+
+    properties:
+      reg:
+        maximum: 0xFFFFFFFE
+        description:
+          Partition identifier. Must be unique within the wgChecker node.
+          The value 0xFFFFFFFF is reserved for unprotected mode and must
+          not be used.
+
+      sifive,wg-region:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description:
+          Protected memory region encoded as a base address and size.
+        items:
+          - description: Upper 32 bits of the base address
+          - description: Lower 32 bits of the base address
+          - description: Upper 32 bits of the region size
+          - description: Lower 32 bits of the region size
+
+      sifive,slot-permissions:
+        $ref: /schemas/types.yaml#/definitions/uint64
+        description: |
+          64-bit WID permission bitmap. Each WID N uses two consecutive bits:
+            - bit[2*N]  : Read  permission for WID N
+            - bit[2*N+1]: Write permission for WID N
+          Set bits grant access.
+
+      sifive,slot-config:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 0x1F
+        description: |
+          Access failure configuration flags for this slot:
+            bit[0] (ER): report read  violations as bus errors
+            bit[1] (EW): report write violations as bus errors
+            bit[2] (IR): report read  violations via interrupt
+            bit[3] (IW): report write violations via interrupt
+            bit[4] (L) : lock this slot against further modification
+          Bits[5:31] are reserved and must be zero.
+
+    required:
+      - reg
+      - sifive,wg-region
+      - sifive,slot-permissions
+      - sifive,slot-config
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - "#access-controller-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    // Example 1: Peripheral device protection
+
+    access-controller@c1000 {
+        compatible = "qemu,wgchecker2", "sifive,wgchecker2";
+        reg = <0xc1000 0x1000>;
+        #access-controller-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <80 4>;
+
+        partition@0 {
+            reg = <0>;
+            sifive,wg-region = <0x0 0x000c0000 0x0 0x00001000>;
+            sifive,slot-permissions = <0x0 0x000000c3>;
+            sifive,slot-config = <0x0f>;
+        };
+    };
+
+  - |
+    // Example 2: DRAM partitioning with multiple regions
+
+    access-controller@40000000 {
+        compatible = "qemu,wgchecker2", "sifive,wgchecker2";
+        reg = <0x40000000 0x1000>;
+        #access-controller-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <82 4>;
+
+        partition@0 {
+            reg = <0>;
+            sifive,wg-region = <0x0 0x80000000 0x0 0x40000000>;
+            sifive,slot-permissions = <0x0 0x000000cf>;
+            sifive,slot-config = <0x0f>;
+        };
+
+        partition@1 {
+            reg = <1>;
+            sifive,wg-region = <0x0 0xc0000000 0x0 0x01000000>;
+            sifive,slot-permissions = <0x0 0x000000cc>;
+            sifive,slot-config = <0x0f>;
+        };
+
+        partition@2 {
+            reg = <2>;
+            sifive,wg-region = <0x0 0xc1000000 0x0 0x3f000000>;
+            sifive,slot-permissions = <0x0 0x000000cf>;
+            sifive,slot-config = <0x0f>;
+        };
+    };
-- 
2.43.7

Re: [RFC PATCH v3 3/3] dt-bindings: access-controllers: Add SiFive WorldGuard Checker

[Yu-Chien Peter Lin]

> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +  - "#access-controller-cells"
> +
> +additionalProperties: false

The wgChecker is always an access-controller provider, never a
consumer. Using additionalProperties:false prevents consumer-side
properties (access-controllers, access-controller-names) from
appearing on a wgChecker node, which unevaluatedProperties:false
would not.

Re: [RFC PATCH v3 3/3] dt-bindings: access-controllers: Add SiFive WorldGuard Checker

[Yu-Chien Peter Lin]

> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +  - "#access-controller-cells"
> +
> +additionalProperties: false

The wgChecker is always an access-controller provider, never a
consumer. Using additionalProperties:false prevents consumer-side
properties (access-controllers, access-controller-names) from
appearing on a wgChecker node, which unevaluatedProperties:false
would not.

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Re: [RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] Placeholder 'TBD' commit hashes are used for the new RISC-V Worlds extensions instead of actual ratified commit hashes.
- [Medium] Enforcing an S-mode extension (`sswid`) to strictly depend on an M-mode extension (`smwiddeleg`) breaks device tree validation for S-mode guest VMs.
- [Medium] The schema fails to enforce the architectural dependency that `smlwid` requires the base `smwid` extension.
--

--- Patch [1]: [RFC PATCH v3 1/3] dt-bindings: riscv: Add Worlds ISA extensions ---
commit 0933aea6342a2dfd4ed22a9a32e7d69364ef3cfc
Author: Yu-Chien Peter Lin <peter.lin@sifive.com>

dt-bindings: riscv: Add Worlds ISA extensions

This commit adds device tree bindings for the RISC-V Worlds ISA extensions
(Smwid, Smlwidlist, Smlwid, Smwiddeleg, Sswid). It also adds extension
dependency rules to the schema.

> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 5ffc40d599c02..0408d11165275 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -181,6 +181,18 @@ properties:
>              changes to interrupts as frozen at commit ccbddab ("Merge pull
>              request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
>  
> +        - const: smlwid
> +          description: |
> +            The standard Smlwid extension for M-mode control of lower
> +            privilege World ID via the mlwid CSR as ratified at commit
> +            TBD ("TBD") of riscv-worlds.

[Severity: Medium]
Does this schema use literal "TBD" placeholders instead of the Git commit
hash of the ratified RISC-V specification? This prevents exact traceability
of the specification version used to define the schema, which is typically
required for RISC-V extensions.

[ ... ]

> @@ -924,6 +953,30 @@ properties:
>          then:
>            contains:
>              const: b
> +      # Smlwidlist depends on Smwid and Smlwid
> +      - if:
> +          contains:
> +            const: smlwidlist
> +        then:
> +          allOf:
> +            - contains:
> +                const: smwid
> +            - contains:
> +                const: smlwid

[Severity: Medium]
Does this schema miss enforcing the architectural dependency that smlwid
requires the base smwid extension? A device tree could declare smlwid
without smwid and silently pass validation, even though that would be an
architecturally invalid hardware configuration.

> +      # Smwiddeleg depends on Smlwid
> +      - if:
> +          contains:
> +            const: smwiddeleg
> +        then:
> +          contains:
> +            const: smlwid
> +      # Sswid depends on Smwiddeleg
> +      - if:
> +          contains:
> +            const: sswid
> +        then:
> +          contains:
> +            const: smwiddeleg

[Severity: Medium]
Will this strict dependency break device tree validation for S-mode guest
VMs?

In virtualized RISC-V environments, a hypervisor provides a device tree to
an S-mode guest VM that intentionally strips out M-mode extensions, since
M-mode is not accessible to the guest. Valid guest device trees containing
sswid might unconditionally fail dt-validate because the M-mode smwiddeleg
extension is stripped.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260812122131.1534906-1-peter.lin@sifive.com?part=1