From: Jason Gunthorpe <jgg@nvidia.com>
To: Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Mostafa Saleh <smostafa@google.com>,
iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org,
David Matlack <dmatlack@google.com>,
Pasha Tatashin <pasha.tatashin@soleen.com>,
patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
Samiullah Khawaja <skhawaja@google.com>
Subject: Re: [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency
Date: Fri, 14 Aug 2026 09:34:17 -0300 [thread overview]
Message-ID: <20260814123417.GB510472@nvidia.com> (raw)
In-Reply-To: <an7UNAA1WlEXG23-@willie-the-truck>
On Fri, Aug 14, 2026 at 09:39:16AM +0100, Will Deacon wrote:
> > Let me try it, it seems like it would make everyone happy.
>
> I was planning to reply yesterday saying something like "Robin previously
> mentioned this one neat trick...", but I didn't get round to it. So yeah,
> if we can implement that, I think we can have one range invalidation
> algorithm to rule them all.
I'm working through it and unfortunately it brings back the CONT
errata issue. This version nicely solves that errata because there is
one RIL that always spans any CONT group.
When we have two RIL it becomes problematic as we can no longer
guarentee that a single RIL fully spans an entire CONT.
I'm also wondering if we are even OK with this errata today? The
current RIL algorithm also does not guarentee the split up RILs will
cover every CONT. This will happen to be true if the input range has
certain properties but I have no idea if the SVA path or even the
proposed CONT iopgtable change guarentees that.
Certainly iommupt will not.
So, if we disable CONT and SVA if this errata is present would anyone
object?
Jason
next prev parent reply other threads:[~2026-08-14 12:34 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 16:26 [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-07 3:04 ` Nicolin Chen
2026-07-07 11:18 ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-07 3:57 ` Nicolin Chen
2026-07-07 16:15 ` Jason Gunthorpe
2026-07-07 17:21 ` Nicolin Chen
2026-07-08 18:43 ` Jason Gunthorpe
2026-07-07 11:24 ` Mostafa Saleh
2026-07-07 18:08 ` Jason Gunthorpe
2026-07-11 17:38 ` Daniel Mentz
2026-07-14 18:41 ` Jason Gunthorpe
2026-07-10 4:06 ` Daniel Mentz
2026-07-10 14:28 ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-07 7:27 ` Nicolin Chen
2026-07-07 19:13 ` Jason Gunthorpe
2026-07-07 21:07 ` Nicolin Chen
2026-07-07 11:45 ` Mostafa Saleh
2026-07-08 0:10 ` Jason Gunthorpe
2026-08-13 13:53 ` Mostafa Saleh
2026-08-13 14:13 ` Jason Gunthorpe
2026-08-13 15:12 ` Mostafa Saleh
2026-08-13 17:05 ` Jason Gunthorpe
2026-08-13 17:25 ` Robin Murphy
2026-08-13 18:01 ` Jason Gunthorpe
2026-08-14 8:39 ` Will Deacon
2026-08-14 12:34 ` Jason Gunthorpe [this message]
2026-07-06 16:26 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-07 7:27 ` Nicolin Chen
2026-07-07 11:46 ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-07 11:52 ` Mostafa Saleh
2026-07-07 14:58 ` Jason Gunthorpe
2026-07-08 9:00 ` Mostafa Saleh
2026-07-08 13:15 ` Jason Gunthorpe
2026-07-07 20:31 ` Nicolin Chen
2026-07-09 12:07 ` Jason Gunthorpe
2026-07-09 19:10 ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-07 11:57 ` Mostafa Saleh
2026-07-08 18:09 ` Jason Gunthorpe
2026-07-07 21:51 ` Nicolin Chen
2026-07-08 18:40 ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-06 18:00 ` Robin Murphy
2026-07-06 19:45 ` Jason Gunthorpe
2026-07-08 1:41 ` Nicolin Chen
2026-07-08 18:27 ` Jason Gunthorpe
2026-07-08 5:29 ` Nicolin Chen
2026-07-09 18:25 ` Jason Gunthorpe
2026-07-09 21:32 ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-07 23:20 ` Nicolin Chen
2026-07-08 0:02 ` Jason Gunthorpe
2026-07-08 2:10 ` Nicolin Chen
2026-07-08 13:05 ` Jason Gunthorpe
2026-07-07 12:25 ` [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Mostafa Saleh
2026-07-07 15:00 ` Jason Gunthorpe
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