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From: Chinmay Rath <rathc@linux.ibm.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	harshpb@linux.ibm.com, milesg@linux.ibm.com
Cc: npiggin@gmail.com, richard.henderson@linaro.org,
	vishalc@linux.ibm.com, tshah@linux.ibm.com,
	shivangu@linux.ibm.com, ojaswin@linux.ibm.com,
	aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com,
	shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com,
	nikhilks@linux.ibm.com, Chinmay Rath <rathc@linux.ibm.com>
Subject: [PATCH 14/29] target/ppc: Convert b{a, l, la} to decode tree
Date: Thu, 20 Aug 2026 19:30:43 +0530	[thread overview]
Message-ID: <20260820140114.327023-15-rathc@linux.ibm.com> (raw)
In-Reply-To: <20260820140114.327023-1-rathc@linux.ibm.com>

From: Ojaswin Mujoo <ojaswin@linux.ibm.com>

Convert b, ba, bl and bla to decode tree specification. The functionality
was tested by comparing the qemu -D log -d op,in_asm output as well as
single stepping gdb to confirm LR was correctly populated only when LK
is set.

Signed-off-by: Ojaswin Mujoo <ojaswin@linux.ibm.com>
Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
---
 target/ppc/insn32.decode               |  7 +++++++
 target/ppc/internal.h                  |  7 -------
 target/ppc/translate.c                 | 24 ------------------------
 target/ppc/translate/branch-impl.c.inc | 24 ++++++++++++++++++++++++
 4 files changed, 31 insertions(+), 31 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 91ece88a70..6a3254aaf6 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -1488,6 +1488,13 @@ MCRF            010011 ... -- ... -- ----- 00000 00000 -       @XL_bfa
 MFBHRBE         011111 ..... ..... ..... 0100101110 -   @XFX_bhrbe
 CLRBHRB         011111 ----- ----- ----- 0110101110 -
 
+# Branch Instructions
+%li             2:24 !function=times_4
+&I_b            li aa:bool lk:bool
+@I_b            ...... ........................ aa:1 lk:1 &I_b li=%li
+
+B               010010 ........................ . .  @I_b
+
 ## Misc POWER instructions
 
 ATTN            000000 00000 00000 00000 0100000000 0
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index a3bb12afd9..a20a0f9f7e 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -197,13 +197,6 @@ EXTRACT_HELPER(L, 16, 2);
 EXTRACT_HELPER(WC, 21, 2);
 EXTRACT_HELPER(PL, 16, 2);
 
-/***                            Jump target decoding                       ***/
-/* Immediate address */
-static inline target_ulong LI(uint32_t opcode)
-{
-    return (opcode >> 0) & 0x03FFFFFC;
-}
-
 static inline uint32_t BD(uint32_t opcode)
 {
     return (opcode >> 0) & 0xFFFC;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a31cda4490..b528cab17d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3089,29 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
     tcg_gen_movi_tl(cpu_lr, nip);
 }
 
-/* b ba bl bla */
-static void gen_b(DisasContext *ctx)
-{
-    target_ulong li, target;
-
-    /* sign extend LI */
-    li = LI(ctx->opcode);
-    li = (li ^ 0x02000000) - 0x02000000;
-    if (likely(AA(ctx->opcode) == 0)) {
-        target = ctx->cia + li;
-    } else {
-        target = li;
-    }
-    if (LK(ctx->opcode)) {
-        gen_setlr(ctx, ctx->base.pc_next);
-        gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL);
-    } else {
-        gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER);
-    }
-    gen_goto_tb(ctx, 0, target);
-    ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 #define BCOND_IM  0
 #define BCOND_LR  1
 #define BCOND_CTR 2
@@ -5366,7 +5343,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
 /* ISA v3.0 changed the extended opcode from 62 to 30 */
 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc
index 9ade0c659a..745f71afd1 100644
--- a/target/ppc/translate/branch-impl.c.inc
+++ b/target/ppc/translate/branch-impl.c.inc
@@ -31,3 +31,27 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
     return true;
 }
 #endif
+
+static bool trans_B(DisasContext *ctx, arg_I_b *a)
+{
+    target_ulong target, li;
+
+    /* sign extend LI */
+    li = (a->li ^ 0x02000000) - 0x02000000;
+
+    if (likely(a->aa == 0)) {
+        target = ctx->cia + li;
+    } else {
+        target = li;
+    }
+    if (a->lk) {
+        gen_setlr(ctx, ctx->base.pc_next);
+        gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL);
+    } else {
+        gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER);
+    }
+    gen_goto_tb(ctx, 0, target);
+    ctx->base.is_jmp = DISAS_NORETURN;
+
+    return true;
+}
-- 
2.55.0



  parent reply	other threads:[~2026-08-20 14:05 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-20 14:00 [PATCH 00/29] target/ppc: Moving instructions to decodetree specification Chinmay Rath
2026-08-20 14:00 ` [PATCH 01/29] target/ppc: Migrate extswsli to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 02/29] target/ppc: Migrate atomic loads " Chinmay Rath
2026-08-20 14:00 ` [PATCH 03/29] target/ppc: Convert cache instructions " Chinmay Rath
2026-08-20 14:00 ` [PATCH 04/29] target/ppc: Move vector merge " Chinmay Rath
2026-08-20 14:00 ` [PATCH 05/29] target/ppc: Move vector pack " Chinmay Rath
2026-08-20 14:00 ` [PATCH 06/29] target/ppc: Move st{b, h, w, d, q}cx " Chinmay Rath
2026-08-20 14:00 ` [PATCH 07/29] target/ppc: convert slw, srw instruction via decode spec Chinmay Rath
2026-08-20 14:00 ` [PATCH 08/29] target/ppc: convert sraw[i] " Chinmay Rath
2026-08-20 14:00 ` [PATCH 09/29] target/ppc: Convert mcrf to decode tree Chinmay Rath
2026-08-20 14:00 ` [PATCH 10/29] target/ppc: Move fixed-point Shift insns to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 11/29] target/ppc: Move fixed-point byte-reversal store " Chinmay Rath
2026-08-20 14:00 ` [PATCH 12/29] target/ppc: Move GPR atomic load/store instructions " Chinmay Rath
2026-08-20 14:00 ` [PATCH 13/29] target/ppc: Move isync instruction " Chinmay Rath
2026-08-20 14:00 ` Chinmay Rath [this message]
2026-08-20 14:00 ` [PATCH 15/29] target/ppc: move various conditional branch insns " Chinmay Rath
2026-08-20 14:00 ` [PATCH 16/29] target/ppc: Fix TRANS* macro variadic arguments handling Chinmay Rath
2026-08-20 14:00 ` [PATCH 17/29] target/ppc: Move wait instruction to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 18/29] target/ppc: Move sleep & friends " Chinmay Rath
2026-08-20 14:00 ` [PATCH 19/29] target/ppc: Refactor sleep and its variants to use a common helper Chinmay Rath
2026-08-20 15:15   ` Miles Glenn
2026-08-20 14:00 ` [PATCH 20/29] target/ppc: Move Condition Register access instructions to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 21/29] target/ppc: Move Condition Register logical " Chinmay Rath
2026-08-20 14:00 ` [PATCH 22/29] target/ppc: make do_ea_calc_ra available for 32 bit builds Chinmay Rath
2026-08-20 14:00 ` [PATCH 23/29] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 24/29] target/ppc: Move VMX integer arithmetic and BCD " Chinmay Rath
2026-08-20 14:00 ` [PATCH 25/29] target/ppc: Move rlwimi, rlwinm " Chinmay Rath
2026-08-20 14:00 ` [PATCH 26/29] target/ppc: Move lmw, stmw " Chinmay Rath
2026-08-20 14:00 ` [PATCH 27/29] target/ppc: Move mfmsr, mtmsr[d] " Chinmay Rath
2026-08-20 14:00 ` [PATCH 28/29] target/ppc: Move byte-reverse " Chinmay Rath
2026-08-20 14:00 ` [PATCH 29/29] target/ppc: Move system call and rfi " Chinmay Rath

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