From: Chinmay Rath <rathc@linux.ibm.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
harshpb@linux.ibm.com, milesg@linux.ibm.com
Cc: npiggin@gmail.com, richard.henderson@linaro.org,
vishalc@linux.ibm.com, tshah@linux.ibm.com,
shivangu@linux.ibm.com, ojaswin@linux.ibm.com,
aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com,
shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com,
nikhilks@linux.ibm.com, Chinmay Rath <rathc@linux.ibm.com>
Subject: [PATCH 04/29] target/ppc: Move vector merge instructions to decodetree
Date: Thu, 20 Aug 2026 19:30:33 +0530 [thread overview]
Message-ID: <20260820140114.327023-5-rathc@linux.ibm.com> (raw)
In-Reply-To: <20260820140114.327023-1-rathc@linux.ibm.com>
From: Aboorva Devarajan <aboorvad@linux.ibm.com>
Move below instructions to decodetree specification:
vmrg{hb, hh, hw, lb, lh, lw} : VX-form
The individual gen_vmrg* functions generated by GEN_VXFORM are
replaced by a shared do_vmrg() helper dispatching to the existing
gen_helper_VMRG* TCG helpers via the TRANS_FLAGS() macro, which
also handles the ALTIVEC facility check.
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Aboorva Devarajan <aboorvad@linux.ibm.com>
Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
---
target/ppc/helper.h | 12 ++++++------
target/ppc/insn32.decode | 9 +++++++++
target/ppc/int_helper.c | 12 ++++++------
target/ppc/translate/vmx-impl.c.inc | 25 +++++++++++++++++++------
target/ppc/translate/vmx-ops.c.inc | 6 ------
5 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 46ad78d1d4..6db917935c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -173,12 +173,12 @@ DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpbfp_dot, void, env, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vmrglb, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vmrglh, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vmrglw, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vmrghb, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vmrghh, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vmrghw, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMRGLB, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMRGLH, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMRGLW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMRGHB, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMRGHH, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMRGHW, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6b1cf9a0a9..8aca8a00c0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -795,6 +795,15 @@ VNOR 000100 ..... ..... ..... 10100000100 @VX
VXOR 000100 ..... ..... ..... 10011000100 @VX
VEQV 000100 ..... ..... ..... 11010000100 @VX
+## Vector Merge Instructions
+
+VMRGHB 000100 ..... ..... ..... 00000001100 @VX
+VMRGHH 000100 ..... ..... ..... 00001001100 @VX
+VMRGHW 000100 ..... ..... ..... 00010001100 @VX
+VMRGLB 000100 ..... ..... ..... 00100001100 @VX
+VMRGLH 000100 ..... ..... ..... 00101001100 @VX
+VMRGLW 000100 ..... ..... ..... 00110001100 @VX
+
## Vector Integer Average Instructions
VAVGSB 000100 ..... ..... ..... 10100000010 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ef4b2e75d6..a3adf746bd 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -950,7 +950,7 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
}
#define VMRG_DO(name, element, access, ofs) \
- void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
ppc_avr_t result; \
int i, half = ARRAY_SIZE(r->element) / 2; \
@@ -963,11 +963,11 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
}
#define VMRG(suffix, element, access) \
- VMRG_DO(mrgl##suffix, element, access, half) \
- VMRG_DO(mrgh##suffix, element, access, 0)
-VMRG(b, u8, VsrB)
-VMRG(h, u16, VsrH)
-VMRG(w, u32, VsrW)
+ VMRG_DO(MRGL##suffix, element, access, half) \
+ VMRG_DO(MRGH##suffix, element, access, 0)
+VMRG(B, u8, VsrB)
+VMRG(H, u16, VsrH)
+VMRG(W, u32, VsrW)
#undef VMRG_DO
#undef VMRG
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 92d6e8c603..00b359f031 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -350,12 +350,25 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
-GEN_VXFORM(vmrghb, 6, 0);
-GEN_VXFORM(vmrghh, 6, 1);
-GEN_VXFORM(vmrghw, 6, 2);
-GEN_VXFORM(vmrglb, 6, 4);
-GEN_VXFORM(vmrglh, 6, 5);
-GEN_VXFORM(vmrglw, 6, 6);
+
+static bool do_vmrg(DisasContext *ctx, arg_VX *a,
+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr ra, rb, rd;
+ REQUIRE_VECTOR(ctx);
+ ra = gen_avr_ptr(a->vra);
+ rb = gen_avr_ptr(a->vrb);
+ rd = gen_avr_ptr(a->vrt);
+ helper(rd, ra, rb);
+ return true;
+}
+
+TRANS_FLAGS(ALTIVEC, VMRGHB, do_vmrg, gen_helper_VMRGHB);
+TRANS_FLAGS(ALTIVEC, VMRGHH, do_vmrg, gen_helper_VMRGHH);
+TRANS_FLAGS(ALTIVEC, VMRGHW, do_vmrg, gen_helper_VMRGHW);
+TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB);
+TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH);
+TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW);
static void trans_vmrgew(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index e28958a126..b8f77d3d2c 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -33,12 +33,6 @@ GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_300(bcds, 0, 27),
-GEN_VXFORM(vmrghb, 6, 0),
-GEN_VXFORM(vmrghh, 6, 1),
-GEN_VXFORM(vmrghw, 6, 2),
-GEN_VXFORM(vmrglb, 6, 4),
-GEN_VXFORM(vmrglh, 6, 5),
-GEN_VXFORM(vmrglw, 6, 6),
GEN_VXFORM_300(vextublx, 6, 24),
GEN_VXFORM_300(vextuhlx, 6, 25),
GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
--
2.55.0
next prev parent reply other threads:[~2026-08-20 14:03 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-20 14:00 [PATCH 00/29] target/ppc: Moving instructions to decodetree specification Chinmay Rath
2026-08-20 14:00 ` [PATCH 01/29] target/ppc: Migrate extswsli to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 02/29] target/ppc: Migrate atomic loads " Chinmay Rath
2026-08-20 14:00 ` [PATCH 03/29] target/ppc: Convert cache instructions " Chinmay Rath
2026-08-20 14:00 ` Chinmay Rath [this message]
2026-08-20 14:00 ` [PATCH 05/29] target/ppc: Move vector pack " Chinmay Rath
2026-08-20 14:00 ` [PATCH 06/29] target/ppc: Move st{b, h, w, d, q}cx " Chinmay Rath
2026-08-20 14:00 ` [PATCH 07/29] target/ppc: convert slw, srw instruction via decode spec Chinmay Rath
2026-08-20 14:00 ` [PATCH 08/29] target/ppc: convert sraw[i] " Chinmay Rath
2026-08-20 14:00 ` [PATCH 09/29] target/ppc: Convert mcrf to decode tree Chinmay Rath
2026-08-20 14:00 ` [PATCH 10/29] target/ppc: Move fixed-point Shift insns to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 11/29] target/ppc: Move fixed-point byte-reversal store " Chinmay Rath
2026-08-20 14:00 ` [PATCH 12/29] target/ppc: Move GPR atomic load/store instructions " Chinmay Rath
2026-08-20 14:00 ` [PATCH 13/29] target/ppc: Move isync instruction " Chinmay Rath
2026-08-20 14:00 ` [PATCH 14/29] target/ppc: Convert b{a, l, la} to decode tree Chinmay Rath
2026-08-20 14:00 ` [PATCH 15/29] target/ppc: move various conditional branch insns to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 16/29] target/ppc: Fix TRANS* macro variadic arguments handling Chinmay Rath
2026-08-20 14:00 ` [PATCH 17/29] target/ppc: Move wait instruction to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 18/29] target/ppc: Move sleep & friends " Chinmay Rath
2026-08-20 14:00 ` [PATCH 19/29] target/ppc: Refactor sleep and its variants to use a common helper Chinmay Rath
2026-08-20 15:15 ` Miles Glenn
2026-08-20 14:00 ` [PATCH 20/29] target/ppc: Move Condition Register access instructions to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 21/29] target/ppc: Move Condition Register logical " Chinmay Rath
2026-08-20 14:00 ` [PATCH 22/29] target/ppc: make do_ea_calc_ra available for 32 bit builds Chinmay Rath
2026-08-20 14:00 ` [PATCH 23/29] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Chinmay Rath
2026-08-20 14:00 ` [PATCH 24/29] target/ppc: Move VMX integer arithmetic and BCD " Chinmay Rath
2026-08-20 14:00 ` [PATCH 25/29] target/ppc: Move rlwimi, rlwinm " Chinmay Rath
2026-08-20 14:00 ` [PATCH 26/29] target/ppc: Move lmw, stmw " Chinmay Rath
2026-08-20 14:00 ` [PATCH 27/29] target/ppc: Move mfmsr, mtmsr[d] " Chinmay Rath
2026-08-20 14:00 ` [PATCH 28/29] target/ppc: Move byte-reverse " Chinmay Rath
2026-08-20 14:00 ` [PATCH 29/29] target/ppc: Move system call and rfi " Chinmay Rath
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