From: Eric Chung <eric.chung@riscstar.com>
To: u-boot-spacemit@groups.io, u-boot@lists.u-boot-project.org,
u-boot@lists.u-boot-project.org
Cc: Tim Ouyang <tim609@andestech.com>,
Leo Liang <leo.liang@sifive.com>, Yao Zi <me@ziyao.cc>,
Huan Zhou <pericycle.cc@gmail.com>,
Tom Rini <trini@konsulko.com>,
Eric Chung <eric.chung@riscstar.com>,
Raymond Mao <raymond.mao@riscstar.com>,
Yixun Lan <dlan@kenrel.org>
Subject: [PATCH 0/2] pinctrl: fix on Spacemit K1 SoC
Date: Mon, 24 Aug 2026 16:13:58 +0800 [thread overview]
Message-ID: <20260824-pinctrl-v1-0-e02ed7e9309f@riscstar.com> (raw)
- Add IO power domain control register programming via APBC block with
ASAR unlocking for dual-voltage GPIO banks (3.3V/1.8V switching)
- Fix drive strength configuration: use FIELD_PREP(), preserve io_type,
return correct pin number, and remove redundant initialization
Signed-off-by: Eric Chung <eric.chung@riscstar.com>
---
Eric Chung (2):
pinctrl: k1: fix drive strength configuration
pinctrl: k1: add IO power domain configuration support
drivers/pinctrl/spacemit/pinctrl-k1.c | 107 +++++++++++++++++++++++++++++++---
1 file changed, 100 insertions(+), 7 deletions(-)
---
base-commit: 6073c36b2c8d39afe3ecc789b281667a3ddebc70
change-id: 20260824-pinctrl-718fe50eb9f8
Best regards,
--
Eric Chung <eric.chung@riscstar.com>
next reply other threads:[~2026-08-24 8:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-24 8:13 Eric Chung [this message]
2026-08-24 8:13 ` [PATCH 1/2] pinctrl: k1: fix drive strength configuration Eric Chung
2026-08-24 8:14 ` [PATCH 2/2] pinctrl: k1: add IO power domain configuration support Eric Chung
2026-09-02 1:52 ` [PATCH 0/2] pinctrl: fix on Spacemit K1 SoC Eric Chung
2026-09-05 11:36 ` Yixun Lan
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