Re: [PATCH v11 08/12] clk: zte: Add zx PLL support infrastructure - sashiko-bot

From: sashiko-bot@kernel.org
To: "Stefan Dösinger" <stefandoesinger@gmail.com>
Cc: conor+dt@kernel.org, linux-phy@lists.infradead.org,
	lee@kernel.org, mfd@lists.linux.dev, vkoul@kernel.org,
	olteanv@gmail.com, devicetree@vger.kernel.org, robh@kernel.org,
	linux-clk@vger.kernel.org, neil.armstrong@linaro.org
Subject: Re: [PATCH v11 08/12] clk: zte: Add zx PLL support infrastructure
Date: Tue, 25 Aug 2026 21:35:54 +0000	[thread overview]
Message-ID: <20260825213554.C20161F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260826-zx29clk-v11-8-f8ad59c6426c@gmail.com>

> This patch adds code to decode and program PLL settings on ZTE's
> zx297520v3 SoC. The PLLs on this SoC are usually programmed to static
> values by the boot loader. The only situation where .set_rate matters is
> dpll, which is not programmed in some cases. The bootloader always sets
> fixed rates though: 624 MHz for mpll, 200 for gpll, 480 for upll.
> 
> Parsing the bootloader-programmed values allows the clock driver to fill
> the clock tree with appropriately clocked parent clocks instead of
> registering fixed clocks with hardcoded rates.
> 
> I only tested the code on zx297520v3. From looking at the hardcoded PLL
> values in the old zx296702 / zx296718 code I believe that these PLLs use
> the same encoding, so the code added by this patch should be reusable
> and the file has a relatively generic name pll-zx.c.
> 
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260826-zx29clk-v11-0-f8ad59c6426c@gmail.com?part=8

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