[PATCH 0/4] arm64: tegra: Add cooling device on Jetson AGX Thor DevKit

[PATCH 0/4] arm64: tegra: Add cooling device on Jetson AGX Thor DevKit

[Thierry Reding]

This set of patches adds the thermal zones for Jetson AGX Thor and sets
up the PWM-controlled fan to act as a cooling device.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Thierry Reding (4):
      arm64: tegra: Add PWM fan on Jetson AGX Orin DevKit
      dt-bindings: thermal: Add Tegra264 header
      arm64: tegra: Add thermal zones for Tegra264
      arm64: tegra: Add cooling device on Jetson AGX Thor DevKit

 arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi     | 32 +++++++++++
 .../boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 65 ++++++++++++++++++++++
 arch/arm64/boot/dts/nvidia/tegra264.dtsi           | 28 ++++++++++
 include/dt-bindings/thermal/nvidia,tegra264-bpmp.h | 20 +++++++
 4 files changed, 145 insertions(+)
---
base-commit: 077f6ea86c7f6467a13134db0f7a7fd175059c26
change-id: 20260817-tegra264-fan-759ee60d0826

Best regards,
--  
Thierry Reding <treding@nvidia.com>

[PATCH 1/4] arm64: tegra: Add PWM fan on Jetson AGX Orin DevKit

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Without a PWM fan device node to actively control the PWM, the fan will
either stop or run at full speed, depending on the state of the PWM when
the controller's clock gets turned off during boot.

One is bad for the system's lifetime and the other is very annoying for
anyone in close proximity to the device, so add the PWM fan in device
tree to fix this.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
index 45f8df9bbfd6..4550e843f513 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
@@ -9,4 +9,17 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	bus@0 {
+		pwm@c6a0000 {
+			status = "okay";
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <77 102 140 192 255>;
+		pwms = <&pwm4 0 40000>;
+		#cooling-cells = <2>;
+	};
 };

-- 
2.55.0

Re: [PATCH 1/4] arm64: tegra: Add PWM fan on Jetson AGX Orin DevKit

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch introduces a platform mismatch by modifying the device tree for the Jetson AGX Thor (Tegra264) while the commit message targets the Jetson AGX Orin (Tegra234). This causes a fatal Device Tree compilation error because the `&pwm4` phandle is not defined in the Tegra264 base tree. Additionally, it maps a PWM node at `0xc6a0000`, which collides with the existing `i2c9` controller's MMIO region in Tegra264.
--

commit 5abc2fdc061c1ce5d90cefc286641978583847de
Author: Thierry Reding <treding@nvidia.com>

arm64: tegra: Add PWM fan on Jetson AGX Orin DevKit

This commit adds a PWM fan device node to actively control the PWM,
preventing the fan from either stopping or running at full speed during boot.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
> index 45f8df9bbfd62..4550e843f513c 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
> @@ -9,4 +9,17 @@ aliases {
>  	chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
> +
> +	bus@0 {
> +		pwm@c6a0000 {

[Severity: Medium]
The commit message targets the Jetson AGX Orin (Tegra234) platform, but this
patch modifies the device tree for the Jetson AGX Thor (Tegra264) in
arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi.

Does this unit address assignment correctly overlay the bus@0/pwm@c6a0000 node?
In the Tegra264 platform, the 0xc6a0000 address is already allocated to the
i2c9 controller (i2c@c6a0000), which creates an MMIO region collision.

> +			status = "okay";
> +		};
> +	};
> +
> +	fan: pwm-fan {
> +		compatible = "pwm-fan";
> +		cooling-levels = <77 102 140 192 255>;
> +		pwms = <&pwm4 0 40000>;

[Severity: Medium]
Will this compile when building the device tree for the Tegra264 platform
with make dtbs?

The &pwm4 phandle used here in the pwm-fan node is not defined in the Tegra264
base device tree. Referencing an undefined label causes a Device Tree Compiler
(dtc) abort.

> +		#cooling-cells = <2>;
> +	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260827-tegra264-fan-v1-0-3c55f0c748b1@nvidia.com?part=1

[PATCH 2/4] dt-bindings: thermal: Add Tegra264 header

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

This header file defines the set of thermal zones exposed by the BPMP on
Tegra264.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 include/dt-bindings/thermal/nvidia,tegra264-bpmp.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h b/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h
new file mode 100644
index 000000000000..b32739691385
--- /dev/null
+++ b/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
+
+#ifndef DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H
+#define DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H
+
+#define TEGRA264_THERMAL_ZONE_TJ_MAX		0
+#define TEGRA264_THERMAL_ZONE_TJ_MIN		1
+#define TEGRA264_THERMAL_ZONE_GPU_AVG		2
+#define TEGRA264_THERMAL_ZONE_CPU_AVG		3
+#define TEGRA264_THERMAL_ZONE_SOC_012_AVG	4
+#define TEGRA264_THERMAL_ZONE_SOC_45_AVG	5
+#define TEGRA264_THERMAL_ZONE_SOC_3_AVG		6
+#define TEGRA264_THERMAL_ZONE_GPU_MAX		7
+#define TEGRA264_THERMAL_ZONE_CPU_MAX		8
+#define TEGRA264_THERMAL_ZONE_SOC_012_MAX	9
+#define TEGRA264_THERMAL_ZONE_SOC_345_MAX	10
+#define TEGRA264_THERMAL_ZONE_TJ_AVG		11
+
+#endif /* DT_BINDINGS_THERMAL_NVIDIA_TEGAR264_BPMP_H */

-- 
2.55.0

Re: [PATCH 2/4] dt-bindings: thermal: Add Tegra264 header

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Typo in the `#endif` include guard trailing comment.
--

commit 925e38b8ce54efbdda094d93d18bb0768571876d
Author: Thierry Reding <treding@nvidia.com>

dt-bindings: thermal: Add Tegra264 header

This header file defines the set of thermal zones exposed by the BPMP on
Tegra264.

> diff --git a/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h b/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h
> new file mode 100644
> index 0000000000000..b327396913856
> --- /dev/null
> +++ b/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h
[ ... ]
> +#define TEGRA264_THERMAL_ZONE_SOC_012_MAX	9
> +#define TEGRA264_THERMAL_ZONE_SOC_345_MAX	10
> +#define TEGRA264_THERMAL_ZONE_TJ_AVG		11
> +
> +#endif /* DT_BINDINGS_THERMAL_NVIDIA_TEGAR264_BPMP_H */

[Severity: Low]
This isn't a bug, but there is a typo in the trailing comment for the
include guard. It reads TEGAR264 instead of TEGRA264.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260827-tegra264-fan-v1-0-3c55f0c748b1@nvidia.com?part=2

Re: [PATCH 2/4] dt-bindings: thermal: Add Tegra264 header

[Conor Dooley]

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On Thu, Aug 27, 2026 at 05:07:51PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> This header file defines the set of thermal zones exposed by the BPMP on
> Tegra264.

Does this need to be a binding, since you're just using it in the dts?
Can it just go into your dts directory insteaD?

Cheers,
Conor.

> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  include/dt-bindings/thermal/nvidia,tegra264-bpmp.h | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h b/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h
> new file mode 100644
> index 000000000000..b32739691385
> --- /dev/null
> +++ b/include/dt-bindings/thermal/nvidia,tegra264-bpmp.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
> +
> +#ifndef DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H
> +#define DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H
> +
> +#define TEGRA264_THERMAL_ZONE_TJ_MAX		0
> +#define TEGRA264_THERMAL_ZONE_TJ_MIN		1
> +#define TEGRA264_THERMAL_ZONE_GPU_AVG		2
> +#define TEGRA264_THERMAL_ZONE_CPU_AVG		3
> +#define TEGRA264_THERMAL_ZONE_SOC_012_AVG	4
> +#define TEGRA264_THERMAL_ZONE_SOC_45_AVG	5
> +#define TEGRA264_THERMAL_ZONE_SOC_3_AVG		6
> +#define TEGRA264_THERMAL_ZONE_GPU_MAX		7
> +#define TEGRA264_THERMAL_ZONE_CPU_MAX		8
> +#define TEGRA264_THERMAL_ZONE_SOC_012_MAX	9
> +#define TEGRA264_THERMAL_ZONE_SOC_345_MAX	10
> +#define TEGRA264_THERMAL_ZONE_TJ_AVG		11
> +
> +#endif /* DT_BINDINGS_THERMAL_NVIDIA_TEGAR264_BPMP_H */
> 
> -- 
> 2.55.0
> 

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Re: [PATCH 2/4] dt-bindings: thermal: Add Tegra264 header

[Thierry Reding]

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On Thu, Aug 27, 2026 at 05:35:28PM +0100, Conor Dooley wrote:
> On Thu, Aug 27, 2026 at 05:07:51PM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > This header file defines the set of thermal zones exposed by the BPMP on
> > Tegra264.
> 
> Does this need to be a binding, since you're just using it in the dts?
> Can it just go into your dts directory insteaD?

I don't think we've ever used these headers outside of DTS files, so,
yes, they could go into the DTS directory.

We've never done that before and there's a bunch of Tegra-specific files
that would be in the same basket. What's your recommendation for any of
the existing headers? Should I move those into the DTS directory, too?
If they are not used outside, that is? Or not worth the churn?

Thierry

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Re: [PATCH 2/4] dt-bindings: thermal: Add Tegra264 header

[Conor Dooley]

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On Thu, Aug 27, 2026 at 07:17:15PM +0200, Thierry Reding wrote:
> On Thu, Aug 27, 2026 at 05:35:28PM +0100, Conor Dooley wrote:
> > On Thu, Aug 27, 2026 at 05:07:51PM +0200, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > > 
> > > This header file defines the set of thermal zones exposed by the BPMP on
> > > Tegra264.
> > 
> > Does this need to be a binding, since you're just using it in the dts?
> > Can it just go into your dts directory insteaD?
> 
> I don't think we've ever used these headers outside of DTS files, so,
> yes, they could go into the DTS directory.
> 
> We've never done that before and there's a bunch of Tegra-specific files
> that would be in the same basket. What's your recommendation for any of
> the existing headers? Should I move those into the DTS directory, too?
> If they are not used outside, that is? Or not worth the churn?

Up to you re: churn I think, but were it my platform I'd probably move
them. 

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Re: [PATCH 2/4] dt-bindings: thermal: Add Tegra264 header

[Krzysztof Kozlowski]

On Thu, Aug 27, 2026 at 06:33:06PM +0100, Conor Dooley wrote:
> On Thu, Aug 27, 2026 at 07:17:15PM +0200, Thierry Reding wrote:
> > On Thu, Aug 27, 2026 at 05:35:28PM +0100, Conor Dooley wrote:
> > > On Thu, Aug 27, 2026 at 05:07:51PM +0200, Thierry Reding wrote:
> > > > From: Thierry Reding <treding@nvidia.com>
> > > > 
> > > > This header file defines the set of thermal zones exposed by the BPMP on
> > > > Tegra264.
> > > 
> > > Does this need to be a binding, since you're just using it in the dts?
> > > Can it just go into your dts directory insteaD?
> > 
> > I don't think we've ever used these headers outside of DTS files, so,
> > yes, they could go into the DTS directory.
> > 
> > We've never done that before and there's a bunch of Tegra-specific files
> > that would be in the same basket. What's your recommendation for any of
> > the existing headers? Should I move those into the DTS directory, too?
> > If they are not used outside, that is? Or not worth the churn?
> 
> Up to you re: churn I think, but were it my platform I'd probably move
> them. 

For Samsung I moved all non-ABI related headers to DTS. I think one more
platform followed. Moving needs to keep old header for some time anyway,
so it's entirely up to you if you/others want to work on that. Like with
every less-important cleanup, the benefit is that correcting old
patterns stops encouraging repeating them.

Best regards,
Krzysztof

[PATCH 3/4] arm64: tegra: Add thermal zones for Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add the thermal zones exposed by the BPMP on Tegra264 so that cooling
devices can be attached to them in board-level DTS files.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 630c20523dcf..5b3082f1ef45 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/memory/nvidia,tegra264.h>
 #include <dt-bindings/power/nvidia,tegra264-bpmp.h>
 #include <dt-bindings/reset/nvidia,tegra264.h>
+#include <dt-bindings/thermal/nvidia,tegra264-bpmp.h>
 
 / {
 	compatible = "nvidia,tegra264";
@@ -4625,6 +4626,33 @@ sound {
 		status = "disabled";
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_CPU_MAX>;
+			status = "disabled";
+		};
+
+		gpu-thermal {
+			thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_GPU_MAX>;
+			status = "disabled";
+		};
+
+		soc012-thermal {
+			thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_SOC_012_MAX>;
+			status = "disabled";
+		};
+
+		soc345-thermal {
+			thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_SOC_345_MAX>;
+			status = "disabled";
+		};
+
+		tj-thermal {
+			thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_TJ_MAX>;
+			status = "disabled";
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

-- 
2.55.0

[PATCH 4/4] arm64: tegra: Add cooling device on Jetson AGX Thor DevKit

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Monitor the TJ thermal zone and use the main PWM fan of the Jetson AGX
Thor Developer Kit to actively cool the device if needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi     | 32 +++++++++++++
 .../boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 52 ++++++++++++++++++++++
 2 files changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
index 58cd81bc33d7..d4c9f45e03c1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
@@ -39,4 +39,36 @@ cmdqv@6200000 {
 			status = "okay";
 		};
 	};
+
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <40>;
+			polling-delay = <1000>;
+			status = "okay";
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <40>;
+			polling-delay = <1000>;
+			status = "okay";
+		};
+
+		soc012-thermal {
+			polling-delay-passive = <40>;
+			polling-delay = <1000>;
+			status = "okay";
+		};
+
+		soc345-thermal {
+			polling-delay-passive = <40>;
+			polling-delay = <1000>;
+			status = "okay";
+		};
+
+		tj-thermal {
+			polling-delay-passive = <40>;
+			polling-delay = <1000>;
+			status = "okay";
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
index 4550e843f513..dd042e57839a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
@@ -22,4 +22,56 @@ fan: pwm-fan {
 		pwms = <&pwm4 0 40000>;
 		#cooling-cells = <2>;
 	};
+
+	thermal-zones {
+		tj-thermal {
+			trips {
+				tj_trip_active0: active-0 {
+					temperature = <80000>;
+					hysteresis = <0>;
+					type = "active";
+				};
+
+				tj_trip_active1: active-1 {
+					temperature = <86000>;
+					hysteresis = <0>;
+					type = "active";
+				};
+
+				tj_trip_active2: active-2 {
+					temperature = <91000>;
+					hysteresis = <0>;
+					type = "active";
+				};
+
+				tj_trip_active3: active-3 {
+					temperature = <100000>;
+					hysteresis = <0>;
+					type = "active";
+				};
+			};
+
+			cooling-maps {
+				map-active-0 {
+					cooling-device = <&fan 0 1>;
+					trip = <&tj_trip_active0>;
+				};
+
+				map-active-1 {
+					cooling-device = <&fan 1 2>;
+					trip = <&tj_trip_active1>;
+				};
+
+				map-active-2 {
+					cooling-device = <&fan 2 3>;
+					trip = <&tj_trip_active2>;
+				};
+
+				map-active-3 {
+					cooling-device = <&fan 3 4>;
+					trip = <&tj_trip_active3>;
+				};
+			};
+		};
+	};
 };

-- 
2.55.0